PCD5003A Datasheet, PDF (21/44 Pages) NXP Semiconductors – Enhanced Pager Decoder for POCSAG

Philips Semiconductors
Enhanced Pager Decoder for POCSAG
Product specification
PCD5003A
7.33 Received call delay
Call reception causes both the periodic interrupt modulus and the counter register to be reset.
Since the periodic interrupt counter runs for another 2.55 seconds after a reset, the received call delay
(in ¹â„₁₀₀ second units) can be determined by reading the counter register.
Table 18 Alert set-up register (04H; write)
BIT (MSB: D7)
D0
D1
D2
D3
D4
D5
D7 and D6⁽¹⁾
VALUE
0
1
0
1
0
1
1
1
1
00
01
10
11
DESCRIPTION
call alert via cadence register
POCSAG call alert (pattern selected by D7, D6)
LOW level acoustic alert (ATL), pulsed vibrator alert (25 Hz)
HIGH level acoustic alert (ATL + ATH), continuous vibrator alert
normal alerts (acoustic and LED)
warbled alerts: 16 Hz (LED: on/off, ATL/ATH: alternate f_AWH, f_AWL)
acoustic alerts enable (ATL, ATH)
vibrator alert enabled (VIB)
LED alert enabled (LED)
POCSAG alert pattern FC = 00, see Fig.9(a)
POCSAG alert pattern FC = 01, see Fig.9(b)
POCSAG alert pattern FC = 10, see Fig.9(c)
POCSAG alert pattern FC = 11, see Fig.9(d)
Note
1. Bits D7 and D6 correspond to function bits 20 and 21 respectively in the address code-word, which designate the
POCSAG call type as shown in Table 1.
D7, D6
handbook, full pagewidth
00
01
10
11
1999 Jan 08
(a)
(b)
(c)
(d)
Fig.9 POCSAG alert patterns.
21
MLC251