P83C557E6 Datasheet, PDF (21/64 Pages) NXP Semiconductors – Single-chip 8-bit microcontroller

Philips Semiconductors
Single-chip 8-bit microcontroller
Product specification
P83C557E6/P80C557E6
Timing
A programmable prescaler is controlled by the bits ADPR1 and
ADPR0 in register ADCON to adapt the conversion time for different
microcontroller clock frequencies.
Table 11 shows conversion times (tconv) for one A/D conversion at
some convenient system clock frequencies (fclk) and ADC prescaler
divisors (m), which are user selectable by the bits ADCON.7/ADPR1
and ADCON.6/ADPR0.
For conversion times outside the limits for tconv the specified ADC
characteristics are not guaranteed; (prohibited conversion times are
put in brackets):
Table 11. Conversion time configuration
examples (tconv/µs)
f_CLK
m
6 MHz
8 MHz
12 MHz
16 MHz
2
26
19.5
[13]
[9.75]
4
50
37.5
25
18.75
6
[74]
[55.5]
37
27.75
8
[98]
[73.5]
49
36.75
Conversion time tconv = (6 m + 1) machine cycles
A conversion time tconv consists of one sample time period (which
equals two bit conversion times), 10 bit conversion time periods and
one machine cycle to store the result.
After result storage an extra initializing time period follows to select
the next analog input channel (according to the contents of SFR
ADPSS), before the input signal is sampled.
Thus the time period between two adjacent conversions within an
autoscan loop is larger than the pure time tconv. This autoscan cycle
time is (7 m) machine cycles.
At the start of an autoscan conversion the time between writing to
SFR ADCON and the first analog input signal sampling depends on
the current prescaler value (m) and the relative time offset between
this write operation and the internal (divided) ADC clock. This gives
a variation range for the A/D conversion start time of ( m / 2 )
machine cycles.
6.6.2 Configuration and Operation
Every A/D conversion is an autoscan conversion. The two user
selectable general operation modes are continuous scan and
one–time scan mode.
The desired analog input port channel/s for conversion is/are
selected by programming A/D input port scan–select bits in SFR
ADPSS. An analog input channel is included in the autoscan loop if
the corresponding bit in ADPSS is 1, a channel is skipped if the
corresponding bit in ADPSS is 0.
An autoscan is always started according to the lowest bit position of
ADPSS that contains a 1.
An autoscan conversion is started by setting the flag ADSST in
register ADCON either by software or by an external start signal at
input pin ADEXS, if enabled. Either no edge (external start totally
disabled), a rising edge or/and a falling edge of ADEXS is selectable
for external conversion start by the bits ADSRE and ADSFE in
register ADCON.
After completion of an A/D conversion the 10–bit result is stored in
the corresponding 10–bit buffer register. Then the next analog input
is selected according to the next higher set bit position in ADPSS,
converted and stored, and so on. When the result of the last
conversion of this autoscan loop is stored, flag ADCON.4/ADINT,
the ADC interrupt flag, is set. It is not cleared by interrupt hardware
– it must be cleared by software.
In continuous scan mode (ADCON.2/ADCSA=1) the ADC start and
status flag ADCON.3/ADSST retains the set state and the autoscan
loop restarts from the beginning. In one–time scan mode
(ADCSA=0) conversions stop after the last selected analog input
was converted, ADINT is set and ADSST is cleared automatically.
ADSST cannot be set (neither externally nor by software) as long as
ADINT=1, i.e. as long as ADINT is set, a new conversion start – by
setting flag ADSST – is inhibited; actually it is only delayed until
ADINT is cleared.
(If a ‘1’ is written to ADSST while ADINT=1, this new value is
internally latched and preserved, not setting ADSST until
ADCON.4/ADINT=0. In this state, a read of SFR ADCON will display
ADCON.3/ADSST=0, because always the effective ADC status is
read.)
Note that under software control the analog inputs can also be
converted in arbitrary order, when one–time scan mode is selected
and in SFR ADPSS only one bit is set at a time. In this case ADINT
is set and ADSST is cleared after every conversion.
6.6.3 Resolution and Characteristics
The ADC system has its own analog supply pins AV_DD and AV_SS. It
is referenced by two special reference voltage input pins sourcing
the resistance ladder of the DAC: AV_ref+ and AV_ref–. The voltage
between AV_REF+ and AV_REF– defines the full–scale range. Due to
the 10–bit resolution the full scale range is divided into 1024 unit
steps. The unit step voltage is 1 LSB, which is typically 5 mV (AV_ref+
= 5.12 V, AV_ref– = 0 V = AV_SS).
The DAC’s resistance ladder has 1023 equally spaced taps,
separated by a unit resistance ‘R’. The first tap is located 0.5 x R
above AV_ref–, the last tap is located 1.5 x R below AV_ref+. This
results in a total ladder resistance of 1024 x R. This structure
ensures that the DAC is monotonic and results in a symmetrical
quantization error. For input voltages between AV_ref– and (AV_ref– +
1/2 LSB) the 10–bit conversion result code will be 00 0000 0000 B =
000H = 0D. For input voltages between (AV_ref+ – 3/2 LSB) and
AV_ref+ the 10–bit conversion result code will be 11 1111 1111 B =
3FFH = 1023D.
The result code corresponding to an analog input voltage (AV_in) can
be calculated from the formula:
ResultĂ Code + 1024
AV_IN * AV_REF*
AV_REF) * AV_REF*
The analog input voltage should be stable when it is sampled for
conversion. At any times the input voltage slew rate must be less
than 10 V/ms (5 V conversion range) in order to prevent an
undefined result.
This maximum input voltage slew rate can be ensured by an RC low
pass filter with R = 2k2 and C = 100 nF. The capacitor between
analog input pin and analog ground pin shall be placed close to the
pins in order to have maximum effect in minimizing input noise
coupling.
1999 Mar 02
21