SAA2003 Datasheet, PDF (20/44 Pages) NXP Semiconductors – Stereo filter and codec

Philips Semiconductors
Stereo filter and codec
Preliminary specification
SAA2003
Table 18 Summary of address registers.
ADDRESS REGISTER
REGISTER
EXPLANATION
0
external settings register
1
codec extended settings
2
serial audio mode control
3
4
5 to 15
fade processor fade rate
fade processor control
not used
BIT
DESCRIPTION
0
1
2
3
0
1
2
3
0
1
2
3
0 to 3
0 to 3
−
mute DAC
attenuate DAC
de-emphasis DAC
clock OK hold mode
slave receive mode
L3/LT mode select
comparator delay bypass
WS/IEC 958 selection
18 bit operation
I²S/EIAJ format
peak detector input select
transparent mode
rate control, 0 to 15
fade command
−
Codec internal settings and status
The settings register is write only, and the status register is read only. The interface protocols for accessing these
registers is shown in Figs 14 and 15.
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L3CLK
L3DATA
89
14 15 0 1
67
MBD627
Fig.14 Codec internal settings write transfer.
May 1994
20