PCD5002 Datasheet, PDF (20/48 Pages) NXP Semiconductors – Advanced POCSAG and APOC-1 Paging Decoder

Philips Semiconductors
Advanced POCSAG and APOC-1 Paging
Decoder
Product specification
PCD5002
Table 16 Index register
ADDRESS⁽¹⁾
00H
00H
01H
02H
03H
04H
05H
05H
06H
07H
08H
09H
0AH
0BH to 0FH
REGISTER FUNCTION
status
control
real time clock: seconds
real time clock:¹â„₁₀₀ second
alert cadence
alert set-up
periodic interrupt modulus
periodic interrupt counter
RAM write address pointer
EEPROM address pointer
RAM read address pointer
RAM data output
EEPROM data input/output
unused
Notes
1. The index register only uses the least significant nibble, the upper 4 bits are ignored.
2. Writing to registers 0B to 0F has no effect, reading produces meaningless data.
ACCESS
R
W
R/W
R/W
W
W
W
R
R
R/W
R/W
R
R/W
note 2
8.26 External interrupt
The PCD5002 can signal events to an external controller
via an interrupt signal at output INT. The interrupt polarity
is programmable via SPF programming. The interrupt
source is shown in the status register.
Interrupts are generated by the following events (more
than one event is possible):
• Call data available for output (bit D2)
• SRAM pointers becoming equal (bit D3)
• Expiry of periodic time-out (bit D7)
• Expiry of alert time-out (bit D4)
• Change of state in out-of-range indicator (bit D5)
• Change of state in battery-low indicator or in receiver
control output RXE (bit D6).
Immediate interrupts are generated by status bits D3,
D4, D6 (RXE monitoring) and D7. Bits D2, D5 and D6
(BAT monitoring) generate interrupts as soon as the
receiver is disabled (RXE = 0).
When call data is available (D2 = 1) but the receiver
remains switched on, an interrupt is generated at the next
sync word position.
The interrupt output INT is reset after completion of a
status read operation.
8.27 Status/Control register
The status/control register consists of two independent
registers, one for reading (status) and one for writing
(control).
The status register shows the current operating condition
of the decoder and the cause(s) of an external interrupt.
The control register activates/deactivates certain
functions. Tables 17 and 18 show the bit allocations of
both registers.
All status bits will be reset after a status read operation
except for the out-of-range, battery-low and receiver
enable indicator bits (see note 1 to Table 17).
1997 Jun 24
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