P32P4911A Datasheet, PDF (20/63 Pages) NXP Semiconductors – PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo

Philips Semiconductors
PRML Read Channel with PR4,
8/9 ENDEC, FWR Servo
Product specification
P32P4911A
The reference frequency is programmed using the M and N registers of the time base generator via the serial port, and
is related to the external reference clock input, FREF, as follows:
F_TBG = FREF * [(M + 1) ÷ (N + 1)]
The M and N values should be chosen with the consideration of phase detector update rate and the external passive
loop filter design. The Data Rate Register must be set to the correct VCO center frequency. The time base generator
PLL responds to any changes to the M and N registers, only after the DR register is updated.
The DR register value, directly affects the following:
center frequency of the time base generator VCO,
center frequency of the data separator VCO,
phase detector gain of the time base generator phase detector,
phase detector gain of the data separator phase detector,
write precompensation
The reference current for the DR DAC is set by an external resistor, RR, connected between the RR pin and ground.
RR = 10.0 kΩ for 42 to 125 Mbit/s data rate range
RR = 12.1 kΩ for 33 to 100 Mbit/s data rate range
Data Separator Circuit Description
The Data Separator circuit provides complete encoding, decoding, and synchronization for 8,9 (0,4,4) GCR data. In data
read mode, the circuit performs clock recovery, code word synchronization, decoding, sync byte detection, descrambling,
and NRZ interface conversion. In the write mode, the circuit generates the VCO sync field, scrambles and converts the
NRZ data into 8,9 (0,4,4) GCR format, precodes the data, and performs write precompensation.
The circuit consists of five major functional blocks; the data synchronizer, 8,9 ENDEC, NRZ scrambler/descrambler, NRZ
interface, and write precompensation.
DATA SYNCHRONIZER
The data synchronizer uses a fully integrated, fast acquisition, PLL to recover the code rate clock from the incoming read
data. To achieve fast acquisition, the data synchronizer PLL uses two separate phase detectors to drive the loop. A
decision-directed phase detector is used in the read mode and phase-frequency detector is used in the idle, servo, and
write modes.
Sampled Read Data
from Adaptive Equalizer
Reference Frequency
from Time Base Generator
VCO
KDS
SAMPLED DATA
PHASE DETECTOR
READ MODE
KDI
PHASE/FREQUENCY
DETECTOR
IDLE/WRITE
MODE
Gm
CHARGE
PUMP
M
Cint ^Cext
12pF
A
KVCO
DS CLK
VCO
1996 Jul 25
Figure 9: Data Synchronizer Phase Locked Loop
20