OM4085 Datasheet, PDF (20/36 Pages) NXP Semiconductors – Universal LCD driver for low multiplex rates

Philips Semiconductors
Universal LCD driver for low multiplex
rates
Product specification
OM4085
Table 5 Definition of OM4085 commands
COMMAND/OPCODE
Mode set
C 1 0 LP E
B M1 M0
Load data pointer
C 0 0 P4 P3 P2 P1 P0
Device select
C 1 1 0 0 A2 A1 A0
Bank select
C11110 I O
Blink
C 1 1 1 0 A BF1 BF0
Table 6 LCD drive mode
LCD DRIVE MODE
Static (1 BP)
1 : 2 MUX (2 BP)
1 : 3 MUX (3 BP)
1 : 4 MUX (4 BP)
OPTIONS
DESCRIPTION
see Table 6
see Table 7
see Table 8
see Table 9
defines LCD drive mode
defines LCD bias configuration
defines display status; the possibility to disable
the display allows implementation of blinking
under external control
defines power dissipation mode
see Table 10
five bits of immediate data, bits P4 to P0, are
transferred to the data pointer to define one of
twenty-four display RAM addresses
see Table 11
three bits of immediate data, bits A0 to A2, are
transferred to the subaddress counter to define
one of eight hardware subaddresses
see Table 12
see Table 13
defines input bank selection (storage of arriving
display data)
defines output bank selection (retrieval of LCD
display data)
the BANK SELECT command has no effect in
1 : 3 and 1 : 4 multiplex drive modes
see Table 14
see Table 15
defines the blinking frequency
selects the blinking mode; normal operation
with frequency set by bits BF1 and BF0, or
blinking by alternation of display RAM banks.
Alternation blinking does not apply in 1 : 3 and
1 : 4 multiplex drive modes
BIT M1
0
1
1
0
BIT M0
1
0
1
0
1997 Feb 25
20