TM-1000 Datasheet, PDF (2/8 Pages) NXP Semiconductors – Programmable Media Processor

TM-1000
a single-chip
multimedia
workhorse
First in the family of TriMedia
processors, the TM-1000 is more
than just an integrated micro-
processor with unusual peripherals.
It is a fluid single-chip computer
system controlled by a small
real-time operating system kernel
running on a VLIW CPU.
PROGRAMMABLE VLIW CPU
At the heart of the TM-1000 is a powerful DSP-like, 32-bit CPU
core. Its VLIW architecture utilizes a five-issue-slot engine. Parallelism
is achieved by simultaneously targeting up to five of the 27 pipelined
functional units in the TM-1000 processor within one clock cycle.
The most common operations have their results available in one clock
cycle; more complex operations have multi-cycle latencies.
Functional units include integer and floating-point arithmetic units
and data-parallel DSP-like units. They can access 128 fully general-
purpose, 32-bit registers during execution. The registers are not sepa-
rated into banks; any operation can use any register for any operand.
TM-1000’s instruction set includes common RISC operations, special
DSP operations that perform powerful SIMD functions, custom mul-
timedia functions, and a full complement of 32-bit, IEEE-compliant,
floating point operations. Both big and little endian byte ordering are
supported.
The TriMedia CPU provides special support for instruction and data
breakpoints, useful in debugging and program development.
SDRAM
IINNSSTTRRUUCCTTIIOONN CCAACCHHEE
ISSUE SLOT 1 ISSUE SLOT 2
ISSUE SLOT 3 ISSUE SLOT 4 ISSUE SLOT 5
FUNCTIONAL UNITS
TRIMEDIA INSTRUCTION EXECUTION
TM-1000’s unique VLIW CPU utilizes separate instruction and data caches,
five issue slots, 27 pipelined functional units, and 128 general-purpose,
32-bit registers to process up to five operations in one clock cycle.