TDA8044 Datasheet, PDF (2/20 Pages) NXP Semiconductors – Satellite demodulator and decoder

Philips Semiconductors
Satellite demodulator and decoder
Product specification
TDA8044
FEATURES
• General features:
– One-chip Digital Video Broadcasting (DVB)
compliant Quadrature Phase Shift Keying (QPSK)
and Binary Phase Shift Keying (BPSK) demodulator
and concatenated Viterbi/Reed-Solomon decoder
with de-interleaver and de-randomizer
(ETS 300 421)
– 3.3 V supply voltage (input pads are 5 V tolerant)
– Standby mode for low power dissipation
– Internal clock PLL to allow low frequency crystal
application and selectable clock frequencies
– Power-on reset module
– Package: QFP100
– Boundary scan test.
• QPSK/BPSK demodulator:
– Interpolator and anti-alias filter to handle a large
range of symbol rates without additional external
filtering
– On-chip AGC of the analog input I and Q baseband
signals or tuner AGC control
– Two on-chip matched Analog-to-Digital Converters
(ADCs; 7 bits)
– Half Nyquist (square root raised-cosine) filter with
selectable roll-off factor
– Large range of symbol frequencies:
0.5 to 45 Msymbols/s for TDA8044 and
0.5 to 30 Msymbols/s for TDA8044A, including
Single Carrier Per Channel (SCPC) function
– Can be used at low channel Signal-to-Noise ratio
(S/N)
– Internal carrier recovery, clock recovery and AGC
loops with programmable loop filters
– Two loop carrier recovery enabling phase tracking of
the incoming symbols
– Software carrier sweep for low symbol rate
applications
– Signal-to-noise ratio estimation
– External indication of demodulator lock.
• Viterbi decoder:
– Rate ¹â„₂ convolutional code based
– Constraint length K = 7 with G₁ = 171_oct and
G₂ = 133_oct; supported puncturing code rates:
1_⁄2, 2_⁄3, 3_⁄4, 4_⁄5, 5_⁄6, 6_⁄7, 7_{⁄8 and} 8_⁄9
– 4 bits input for ‘soft decision’ for both I and Q
– Truncation length: 144
– Automatic synchronization
– Channel Bit Error Rate (BER) estimation
– External indication of Viterbi sync lock
– Differential decoding optional.
• Reed-Solomon (RS) decoder:
– (204, 188, T = 8) Reed-Solomon code
– Automatic (I²C-bus configurable) synchronization of
bytes, transport packets and frames
– Internal convolutional de-interleaving (I = 12; using
internal memory)
– De-randomizer based on Pseudo Random Bit
Sequence (PRBS)
– External indication of Register Select (RS) decoder
sync lock
– External indication of uncorrectable error (transport
error indicator is set)
– External indication of corrected byte
– Indication of the number of lost blocks
– Indication of the number of corrected blocks.
• Interface:
– I²C-bus interface to initialize and monitor the
demodulator and Forward Error Correction (FEC)
decoder; when no I²C-bus usage, default mode is
defined
– Programmable interrupt facility
– 6 bits I/O expander for flexible access to and from the
I²C-bus
– Switchable I²C-bus loop-through to suppress I²C-bus
crosstalk in the tuner
– DiSEqC level 1.X support for dish control applications
– 3-state mode for transport stream outputs.
APPLICATIONS
• Digital satellite TV: demodulation and Forward Error
Correction (FEC).
2000 Feb 21
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