TDA6404 Datasheet, PDF (2/32 Pages) NXP Semiconductors – 5 V mixer/oscillator-PLL synthesizers for hyperband tuners

Philips Semiconductors
5 V mixer/oscillator-PLL synthesizers
for hyperband tuners
Product specification
TDA6404; TDA6405;
TDA6405A
FEATURES
• Single chip 5 V mixer/oscillator-PLL synthesizer for
hyperband tuners
• I²C-bus protocol
• 3 PNP band switch buffers (25 mA)
• 33 V tuning voltage output
• In-lock detector
• 5-level Analog-to-Digital Converter (ADC)
• 15-bit programmable divider
• Programmable reference divider ratio
(512, 640 or 1024)
• Programmable charge pump current
• Balanced mixer with a common emitter input for VHF
(single input)
• Balanced mixer with a common base input for UHF
(double input)
• 4-pin common emitter oscillator for VHF
• 4-pin common emitter oscillator for UHF
• IF amplifier with a low output impedance to drive a SAW
filter directly (≈2 kΩ load)
• Low power, low radiation, small size
APPLICATIONS
• Hyperband tuners for Europe using a 2-band
mixer/oscillator in a switched concept.
GENERAL DESCRIPTION
The TDA6404, TDA6405 and TDA6405A are
programmable 2-band mixer/oscillator-PLL synthesizers
intended for VHF/UHF and hyperband tuners (see Fig.1).
The devices include two double balanced mixers and two
oscillators for the VHF and UHF band, an IF amplifier and
a PLL synthesizer. With proper oscillator application and
by using a switchable inductor to split the VHF band into
two sub-bands (the full VHF/UHF and hyperband) the TV
bands can be covered.
Two pins are available between the mixer output and the
IF amplifier input to enable IF filtering for improved signal
handling. Three PNP ports are provided for band
switching. Band selection is made according to the band
switch bits VHFL, VHFH and UHF.
The PLL synthesizer consists of a divide-by-eight
prescaler, a 15-bit programmable divider, a 4 MHz crystal
oscillator and its programmable reference divider and a
phase comparator combined with a charge pump which
drives the tuning amplifier, including 33 V output.
Depending on the reference divider ratio (512, 640
or 1024), the phase comparator operates at 7.8125 kHz,
6.25 kHz or 3.90625 kHz.
The devices are controlled according to the I²C-bus
format. The in-lock detector bit FL is set to logic 1 when the
loop is locked and is read on the SDA line (status byte)
during a read operation. The ADC input is available for
digital Automatic Frequency Control (AFC). The ADC code
is read during a read operation on the I²C-bus
(see Table 9). In test mode, pin ADC is used as a test
output for f_REF and ¹â„₂f_DIV.
When the charge pump current switch mode is activated
and the loop is phase-locked the charge pump current
value is automatically switched to LOW. This is to improve
carrier-to-noise ratio. The status of this feature can be read
in the ACPS flag during a read operation on the I²C-bus
(see Table 7).
Five serial bytes (including address byte) are required for
the I²C-bus format to address the devices, select the VCO
frequency, program the three PNP ports, set the charge
pump current and to set the reference divider ratio.
The devices have four independent I²C-bus addresses
which can be selected by applying a specific voltage on the
AS input (see Table 4).
1999 Jan 13
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