LPC2468_15 Datasheet, PDF(2/85 Page) NXP Semiconductors – Single-chip 16-bit/32-bit micro; 512 kB flash, Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface

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LPC2468_15 Datasheet, PDF (2/85 Pages) NXP Semiconductors – Single-chip 16-bit/32-bit micro; 512 kB flash, Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface

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NXP Semiconductors

LPC2468

Single-chip 16-bit/32-bit micro

LPC2468

Product data sheet

ïµ 16 kB SRAM for general purpose DMA use also accessible by the USB.

ïµ 2 kB SRAM data storage powered from the Real-Time Clock (RTC) power domain.

ï® Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet

DMA, USB DMA, and program execution from on-chip flash with no contention.

ï® EMC provides support for asynchronous static memory devices such as RAM, ROM

and flash, as well as dynamic memories such as single data rate SDRAM.

ï® Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.

ï® General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP,

I2S-bus, and SD/MMC interface as well as for memory-to-memory transfers.

ï® Serial Interfaces:

ïµ Ethernet MAC with MII/RMII interface and associated DMA controller. These

functions reside on an independent AHB.

ïµ USB 2.0 full-speed dual port device/host/OTG controller with on-chip PHY and

associated DMA controller.

ïµ Four UARTs with fractional baud rate generation, one with modem control I/O, one

with IrDA support, all with FIFO.

ïµ CAN controller with two channels.

ïµ SPI controller.

ïµ Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate

for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA controller.

ïµ Three I2C-bus interfaces (one with open-drain and two with standard port pins).

ïµ I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with

the GPDMA.

ï® Other peripherals:

ïµ SD/MMC memory card interface.

ïµ 160 General purpose I/O pins with configurable pull-up/down resistors.

ïµ 10-bit ADC with input multiplexing among 8 pins.

ïµ 10-bit DAC.

ïµ Four general purpose timers/counters with 8 capture inputs and 10 compare

outputs. Each timer block has an external count input.

ïµ Two PWM/timer blocks with support for three-phase motor control. Each PWM has

an external count inputs.

ïµ RTC with separate power domain. Clock source can be the RTC oscillator or the

APB clock.

ïµ 2 kB SRAM powered from the RTC power pin, allowing data to be stored when the

rest of the chip is powered off.

ïµ WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,

the RTC oscillator, or the APB clock.

ï® Standard ARM test/debug interface for compatibility with existing tools.

ï® Emulation trace module supports real-time trace.

ï® Single 3.3 V power supply (3.0 V to 3.6 V).

ï® Four reduced power modes: idle, sleep, power-down, and deep power-down.

ï® Four external interrupt inputs configurable as edge/level sensitive. All pins on port 0

and port 2 can be used as edge sensitive interrupt sources.

ï® Processor wake-up from Power-down mode via any interrupt able to operate during

Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet

wake-up interrupt, CAN bus activity, port 0/2 pin interrupt).

All information provided in this document is subject to legal disclaimers.

Rev. 6.2 â 11 January 2013

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