HEF4522B Datasheet, PDF (2/10 Pages) NXP Semiconductors – Programmable 4-bit BCD down counter

Philips Semiconductors
Programmable 4-bit BCD down counter
Product specification
HEF4522B
MSI
DESCRIPTION
The HEF4522B is a synchronous programmable 4-bit
BCD down counter with an active HIGH and an active
LOW clock input (CP₀, CP₁), an asynchronous parallel
load input (PL), four parallel inputs (P₀ to P₃), a cascade
feedback input (CF), four buffered parallel outputs (O₀ to
O₃), a terminal count output (TC) and an overriding
asynchronous master reset input (MR).
This device is a programmable, cascadable down counter
with a decoded TC output for divide-by-n applications. In
single stage applications the TC output is connected to PL.
CF allows cascade divide-by-n operation with no
additional gates required.
Information on P₀ to P₃ is loaded into the counter while PL
is HIGH, independent of all other input conditions except
MR, which must be LOW. When PL and CP₁ are LOW, the
counter advances on a LOW to HIGH transition of CP₀.
When PL is LOW and CP₀ is HIGH, the counter advances
on a HIGH to LOW transition of CP₁. TC is HIGH when the
counter is in the zero state (O₀ = O₁ = O₂ = O₃ = LOW)
and CF is HIGH and PL is LOW. A HIGH on MR resets the
counter (O₀ to O₃ = LOW) independent of other input
conditions.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
Fig.1 Functional diagram.
FAMILY DATA, I_DD LIMITS category MSI
See Family Specifications
January 1995
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