GTL2010 Datasheet, PDF (2/6 Pages) NXP Semiconductors – 10-bit GTL Processor Voltage Clamp

Philips Semiconductors
10-bit GTL Processor Voltage Clamp
Product specification
GTL2010
FEATURES
• Direct interface with TTL level
• 6.5Ω ON-state connection between port S_n and D_n
DESCRIPTION
The GTL2010 is a high speed 10-bit voltage clamp. The low
ON-state resistance of the clamp allows connections to be made
with minimal propagation delay.
The device is organized as one 10-bit voltage clamp. When S or D
is low, the clamp is in the ON–state and a low resistance connection
exists between the S and D ports. When S port and D port are high,
the clamp is in the OFF-state and a very high impedance exists
between the S and D ports. When port D is high, the voltage on the
S port is clamped to the applied reference voltage on the GREF
port.
PIN CONFIGURATION
GND 1
S_REF 2
S₁ 3
S₂ 4
S₃ 5
S₄ 6
S₅ 7
S₆ 8
S₇ 9
S_{8 10}
S₉ 11
S₁₀ 12
24 ^GREF
23 DREF
22 D₁
21 D2
20 D₃
19 D₄
18 D₅
17 ^D6
16 D7
15 D8
14 D9
13 D₁₀
QUICK REFERENCE DATA
SYMBOL
PARAMETER
t_PLH
C_OFF
Propagation delay
Sn to Dn
Channel capacitance (OFF-state)
CONDITIONS
T_amb = 25°C; GND = 0V
V_DD1 = 3.3V; V_DD2 = 2.5V;
V_REF = 1.5V; unloaded
V_S = 1.5V
SA00527
TYPICAL
1.5
7.5
UNIT
ns
pF
ORDERING INFORMATION
PACKAGES
24-Pin Plastic TSSOP Type II
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
0°C to +85°C
GTL2010 PW
NORTH AMERICA
GTL2010PW DH
DWG NUMBER
SOT355–1
PIN DESCRIPTION
PIN NUMBER
SYMBOL
1
GND
2
3 – 12
13 – 22
23
S_REF
S_n
D_n
D_REF
24
G_REF
FUNCTION TABLE
S_N
L
H
H = High voltage level
L = Low voltage level
Z = High impedance “off ” state
NAME AND FUNCTION
Ground (0V)
Source of reference
transistor
Port S₁ to Port S₁₀
Port D₁ to Port D₁₀
Drain of reference
transistor
Gate of reference
transistor
D_N
L
H
CLAMP SCHEMATIC
D_REF
G_REF
D₁
S_REF
S₁
D₁₀
S₁₀
SA00526
1999 Apr 05
2
853-2153 21178