GTL2006 Datasheet, PDF (2/14 Pages) NXP Semiconductors – 13-bit GTL-/GTL/GTL+ to LVTTL translator

Philips Semiconductors
13-bit GTL–/GTL/GTL+ to LVTTL translator
Product data
GTL2006
FEATURES
• Operates as a GTL–/GTL/GTL+ to LVTTL sampling receiver or
LVTTL to GTL–/GTL/GTL+ driver
• 3.0 V to 3.6 V operation
• LVTTL I/O not 5 V tolerant
• Series termination on the LVTTL outputs of 30 Ω
• ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 250 V CDM per JESD22-C101
• Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 500 mA
• Package offered: TSSOP28
DESCRIPTION
The GTL2006 is a 13-bit translator to interface between the 3.3 V
LVTTL chip set I/O and the Xeon™ processor GTL–/GTL/GTL+ I/O.
The GTL2006 is designed for platform health management in dual
processor applications.
PIN CONFIGURATION
V_REF 1
1AO 2
28 V_CC
27 1BI
2AO 3
26 2BI
5A 4
25 7BO1
6A 5
24 7BO2
8AI 6
23 8BO
11BI 7
22 11BO
11A 8
21 5BI
9BI 9
20 6BI
3AO 10
19 3BI
4AO 11
18 4BI
10AI1 12
10AI2 13
17 10BOI
16 10BO2
GND 14
15 9AO
SW01091
Figure 1. Pin configuration
QUICK REFERENCE DATA
SYMBOL
PARAMETER
t_PLH
Propagation delay
t_PHL
An to Bn or Bn to An
C_I/O
I/O pin capacitance
PIN DESCRIPTION
PIN NUMBER SYMBOL
1
2–6, 8,
10–13, 15
V_REF
nAn
7, 9, 16,
17–27
nBn
14
GND
28
V_CC
NAME AND FUNCTION
GTL reference voltage
Data inputs/outputs
(LVTTL)
Data inputs/outputs
(GTL–/GTL/GTL+)
Ground (0 V)
Positive supply voltage
CONDITIONS
T_amb = 25 °C
C_L = 50 pF; V_CC = 3.3 V
Outputs disabled; V_I/O = 0 V or 3.0 V
TYPICAL
B to A
A to B
5.5
5.5
7.8
4.5
UNIT
ns
pF
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
TOPSIDE MARK
28-Pin Plastic TSSOP
–40 °C to +85 °C
GTL2006PW
GTL2006
Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
DWG NUMBER
SOT361-1
2004 Jun 21
2