GTL2005 Datasheet, PDF (2/8 Pages) NXP Semiconductors – Quad GTL/GTL to LVTTL/TTL bidirectional non-latched translator

Philips Semiconductors
Quad GTL/GTL+ to LVTTL/TTL
bidirectional non-latched translator
Product specification
GTL2005
FEATURES
• Operates as a quad GTL/GTL+ sampling receiver or as a
LVTTL/TTL to GTL/GTL+ driver
• Quad bidirectional bus interface
• Live insertion/extraction permitted
• Latch-up protection exceeds 500 mA per JESD78
• ESD protection exceeds 2000 V HBM per JESD22-A114, and
1000 V CDM per JESD22-CC101
DESCRIPTION
The GTL2005 is a quad translating transceiver designed for 3.3 V
system interface with a GTL/GTL⁺ bus.
The direction pin allows the part to function as either a GTL to TTL
sampling receiver or as a TTL to GTL interface.
PIN CONFIGURATION
DIR 1
A0 2
A1 3
GTLREF 4
A2 ₅
A3 6
GND ₇
14 V_CC
13 B0
12 B1
11 GND
10 B2
9 _B3
8 GND
SW00321
QUICK REFERENCE DATA
SYMBOL
PARAMETER
t_PLH
Propagation delay
t_PHL
An to Bn or Bn to An
C_IN
Input capacitance DIR
C_I/O
I/O pin capacitance
CONDITIONS
T_amb = 25°C
C_L = 50 pF; V_CC = 3.3 V
V_I = 0 V or V_CC
Outputs disabled; V_I/O = 0 V or 3.0 V
TYPICAL
B to A A to B
2.1
4.1
1.9
4.3
3.0
3.0
7.8
4.5
UNIT
ns
pF
pF
ORDERING INFORMATION
PACKAGES
14-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
ORDER CODE
GTL2005 PW DH
DWG NUMBER
SOT402-1
PIN DESCRIPTION
PIN NUMBER SYMBOL
1
DIR
2, 3, 5, 6
A0 – A3
13, 12, 10, 9 B0 – B3
4
GTLREF
7, 8, 11
GND
14
V_CC
NAME AND FUNCTION
Direction control input
Data inputs/outputs (A side, GTL)
Data inputs/outputs (B side, TTL)
GTL reference voltage
Ground (0 V)
Positive supply voltage
FUNCTION TABLE
INPUT
INPUT/OUTPUT
DIR
B
A
H
Inputs
Bn = An
L
An = Bn
Inputs
H = HIGH voltage level
L = LOW voltage level
LOGIC SYMBOL
A0
A1
A2
A3
GTLREF
B0
B1
B2
B3
DIR
SW00320
1999 Sep 17
2
853–2171 22353