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| BLM2425M7S60P_15 Datasheet, PDF (2/12 Pages) NXP Semiconductors – LDMOS 2-stage power MMIC | |||
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NXP Semiconductors
2. Pinning information
2.1 Pinning
SLQLQGH[
BLM2425M7S60P
LDMOS 2-stage power MMIC
9'6 $
9*6 $
9*6 $
5)B,1B$
9*6 $
9*6 $
QF
QF
9*6 %
9*6 %
5)B,1B%
9*6 %
9*6 %
9'6 %
5)B287B$9'6 $
5)B287B%9'6 %
DDD
Fig 1.
Transparent top view
The exposed backside of the package is the ground terminal of the device.
Pin configuration
2.2 Pin description
Table 2. Pin description
Symbol
VDS(A1)
VGS(A2)
RF_IN_A
VGS(A1)
n.c.
n.c.
VGS(B1)
RF_IN_B
VGS(B2)
VDS(B1)
RF_OUT_B/VDS(B2)
RF_OUT_A/VDS(A2)
GND
Pin Description
1
drain-source voltage of stage A1
2, 3 gate-source voltage of stage A2
4
RF input path A
5, 6 gate-source voltage of stage A1
7
not connected
8
not connected
9, 10 gate-source voltage of stage B1
11 RF input path of B
12, 13 gate-source voltage of stage B2
14 drain-source voltage of stage B1
15 RF output path B / drain source voltage of stage B2
16 RF output path A / drain source voltage of stage A2
flange RF ground
BLM2425M7S60P
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 â 18 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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