BLF10H6600P_15 Datasheet, PDF (2/18 Pages) NXP Semiconductors – Power LDMOS transistor

NXP Semiconductors
BLF10H6600P; BLF10H6600PS
Power LDMOS transistor
2. Pinning information
Table 2. Pinning
Pin
Description
BLF10H6600P (SOT539A)
1
drain1
2
drain2
3
gate1
4
gate2
5
source
BLF10H6600PS (SOT539B)
1
drain1
2
drain2
3
gate1
4
gate2
5
source
[1] Connected to flange.
3. Ordering information
Simplified outline Graphic symbol
12
1
5
34
[1]
3
5
4
2
sym117
12
1
5
34
[1]
3
5
4
2
sym117
Table 3. Ordering information
Type number Package
Name Description
BLF10H6600P -
flanged balanced ceramic package; 2 mounting holes;
4 leads
BLF10H6600PS -
earless flanged balanced ceramic package; 4 leads
Version
SOT539A
SOT539B
4. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min Max Unit
V_DS
drain-source voltage
V_GS
gate-source voltage
T_stg
storage temperature
T_j
junction temperature
-
110
V
0.5 +11
V
65 +150 C
[1] _-
225
C
[1] Continuous use at maximum temperature will affect the reliability. For details refer to the on-line MTF
calculator.
BLF10H6600P_BLF10H6600PS
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 20 June 2013
© NXP B.V. 2013. All rights reserved.
2 of 18