74LV4060 Datasheet, PDF (2/18 Pages) NXP Semiconductors – 14-stage binary ripple counter with oscillator

Philips Semiconductors
14-stage binary ripple counter with oscillator
Product specification
74LV4060
FEATURES
• Wide operating voltage: 1.0 to 5.5 V
• Optimized for Low Voltage applications: 1.0 to 3.6 V
• Accepts TTL input levels between V_CC = 2.7 V and V_CC = 3.6 V
• Typical V_OLP (output ground bounce) < 0.8 V at V_CC = 3.3 V,
T_amb = 25°C.
• Typical V_OHV (output V_OH undershoot) > 2 V at V_CC = 3.3 V, T_amb
= 25°C.
• All active components on chip
• RC or crystal oscillator configuration
• Output capability: standard (except for R_TC and C_TC)
• I_CC category: MSI
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25°C; t_r = t_f < 2.5 ns
APPLICATIONS
• Control Counters
• Timers
• Frequency Dividers
• Time-delay circuits
DESCRIPTION
The 74LV4060 is a low-voltage Si-gate CMOS device and is pin and
function compatible with the 74HC/HCT4060.
The 74LV4060 is a 14-stage ripple-carry counter/divider and
oscillator with three oscillator terminals (RS, R_TC and C_TC), ten
buffered outputs (Q₃ to Q₉ and Q₁₁ to Q₁₃) and an overriding
asynchronous master reset (MR). The oscillator configuration allows
design of either RC or crystal oscillator circuits. The oscillator may
be replaced by an external clock signal at input RS. In this case,
keep the oscillator pins (R_TC and C_TC) floating.
The counter advances on the negative-going transition of RS. A
HIGH level on MR resets the counter (Q₃ to Q₉ and Q₁₁ to
Q₁₃ = LOW), independent of the other input conditions.
SYMBOL
t_PHL/t_PLH
t_PHL
f_max
C₁
C_PD
PARAMETER
CONDITIONS
Propagation delay
RS to Q₃
Q_n to Q_n+1
MR to Q_n
Maximum clock frequency
C_L = 15 pF
V_CC = 3.3 V
Input capacitance
Notes 1, 2 and 3
Power dissipation capacitance per package
TYPICAL
29
6
16
99
3.5
40
UNIT
ns
MHz
pF
pF
NOTES:
1. C_PD is used to determine the dynamic power
dissipation (P_D in mW)
P_D = C_PD x V_CC2 x f_i + S (C_L x V_CC2 x f_o) where:
f_i = input frequency in MHz; C_L = output load capacity in pF;
f_o = output frequency in MHz; V_CC = supply voltage in V;
S (C_L x V_CC2 x f_o) = sum of the outputs.
2. The condition is V₁ = GND to V_CC
3. For formula on dynamic power dissipation, see the
following pages.
ORDERING INFORMATION
PACKAGES
16-Pin Plastic DIL
16-Pin Plastic SO
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
–40°C to +125°C
74LV4060 N
–40°C to +125°C
74LV4060 D
–40°C to +125°C
74LV4060 DB
–40°C to +125°C
74LV4060 PW
NORTH AMERICA
74LV4060 N
74LV4060 D
74LV4060 DB
74LV4060PW DH
PKG. DWG. #
SOT38-4
SOT109-1
SOT338-1
SOT403-1
1998 Jun 23
2
853-2076 19619