74HC_HCT85_CNV_15 Datasheet, PDF (2/9 Pages) NXP Semiconductors – 4-bit magnitude comparator

Philips Semiconductors
4-bit magnitude comparator
Product specification
74HC/HCT85
FEATURES
• Serial or parallel expansion without extra gating
• Magnitude comparison of any binary words
• Output capability: standard
• I_CC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT85 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT85 are 4-bit magnitude comparators that
can be expanded to almost any length. They perform
comparison of two 4-bit binary, BCD or other monotonic
codes and present the three possible magnitude results at
the outputs (Q_A>B, Q_A=B and Q_A<B). The 4-bit inputs are
weighted (A₀ to A₃ and B₀ to B₃), where A₃ and B₃ are the
most significant bits.
The operation of the “85” is described in the function table,
showing all possible logic conditions. The upper part of the
table describes the normal operation under all conditions
that will occur in a single device or in a series expansion
scheme. In the upper part of the table the three outputs are
mutually exclusive. In the lower part of the table, the
outputs reflect the feed forward conditions that exist in the
parallel expansion scheme.
For proper compare operation the expander inputs (I_A>B,
I_A=B and I_A<B) to the least significant position must be
connected as follows: I_A<B = I_A>B = = LOW and
I_A=B = HIGH.
For words greater than 4-bits, units can be cascaded by
connecting outputs Q_A<B, Q_A>Β and Q_A=B to the
corresponding inputs of the significant comparator.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL
PARAMETER
CONDITIONS
t_PHL/ t_PLH
C_I
C_PD
propagation delay
A_n, B_n to Q_A>B, Q_A<B
A_n, B_n to Q_A=B
I_A<B,, I_A=B, I_A>B to Q_A<B, Q_A>B
I_A=B to Q_A=B
input capacitance
power dissipation capacitance per package
C_L = 15 pF; V_CC = 5 V
notes 1 and 2
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + ∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz
f_o = output frequency in MHz
∑ (C_L × V_CC2 × f_o) = sum of outputs
C_L = output load capacitance in pF
V_CC = supply voltage in V
2. For HC the condition is V_I = GND to V_CC
For HCT the condition is V_I = GND to V_CC − 1.5 V
TYPICAL
HC HCT
UNIT
20
22
ns
18
20
ns
15
15
ns
11
15
ns
3.5 3.5 pF
18
20
pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2