74HC_HCT4514_CNV_15 Datasheet, PDF (2/9 Pages) NXP Semiconductors – 4-to-16 line decoder/demultiplexer with input latches

Philips Semiconductors
4-to-16 line decoder/demultiplexer with
input latches
Product specification
74HC/HCT4514
FEATURES
• Non-inverting outputs
• Output capability: standard
• I_CC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4514 are high-speed Si-gate CMOS
devices and are pin compatible with “4514” of the “4000B”
series. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT4514 are 4-to-16 line
decoders/demultiplexers having four binary weighted
address inputs (A₀ to A₃), with latches, a latch enable input
(LE), and an active LOW enable input (E). The 16 outputs
(Q₀ to Q₁₅) are mutually exclusive active HIGH. When LE
is HIGH, the selected output is determined by the data on
A_n. When LE goes LOW, the last data present at A_n are
stored in the latches and the outputs remain stable. When
E is LOW, the selected output, determined by the contents
of the latch, is HIGH. At E HIGH, all outputs are LOW. The
enable input (E) does not affect the state of the latch.
When the “4514” is used as a demultiplexer, E is the data
input and A₀ to A₃ are the address inputs.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL
PARAMETER
CONDITIONS
t_PHL/ t_PLH
C_I
C_PD
propagation delay A_n to Q_n
input capacitance
power dissipation capacitance per package
C_L = 15 pF; V_CC = 5 V
notes 1 and 2
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i +∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz
f_o = output frequency in MHz
∑ (C_L × V_CC2 × f_o) = sum of outputs
C_L = output load capacitance in pF
V_CC = supply voltage in V
2. For HC the condition is V_I = GND to V_CC
For HCT the condition is V_I = GND to V_CC − 1.5 V
TYPICAL
HC
23
3.5
44
HCT
26
3.5
45
UNIT
ns
pF
pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
September 1993
2