74HCT7273 Datasheet, PDF (2/20 Pages) NXP Semiconductors – Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs

Philips Semiconductors
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
Product specification
74HCT7273
FEATURES
• ESD protection:
HBM EIA/JESD22-A114-A
Exceeds 2000 V
MM EIA/JESD22-A115-A
Exceeds 200 V
• Ideal buffer for MOS
microprocessor or memory
• Eight positive edge-triggered
D-type flip-flops
• Common clock and master reset
• Output capability: standard (open
drain)
• I_CC category: MSI.
DESCRIPTION
The 74HCT7273 is a high-speed SI-gate CMOS device and is pin compatible
with Low power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard no 7A.
The 74HCT7273 has eight edge-triggered D-type flip-flops with individual D
inputs and Q outputs. The common Clock (CP) and Master Reset (MR) inputs
load and reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding output (Q_n) of the flip-flop.
A LOW level on the MR input forces all outputs LOW, independently of the clock
or data inputs.
The device is useful for applications requiring true outputs only and clock and
master reset inputs that are common to all storage elements.
The 74HCT7273 has open-drain N-outputs, which are clamped by a diode
connected to V_CC. When a HIGH is clocked in the flip-flop, the output comes in
the high-impedance OFF-state. The output may now be pulled to any voltage
between GND and V_Omax. This allows the device to be used as a LOW-to-HIGH
or HIGH-to-LOW level shifter. For digital operation and OR-tied output
applications, the device must have a pull-up resistor to establish a logic HIGH
level.
QUICK REFERENCE DATA
Ground = 0 V; T_amb = 25 °C; t_r = t_f = 6.0 ns.
SYMBOL
PARAMETER
t_PZL/t_PLZ
f_max
C_I
C_PD
propagation delay
CP to Q_n
MR to Q_n
maximum clock frequency
input capacitance
power dissipation capacitance
CONDITIONS
C_L = 50 pF; V_CC = 4.5 V
C_L = 50 pF; f = 1 MHz; notes 1 and 2
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW).
P_D = C_PD × V_CC2 × f_i + ∑ (C_L × V_CC2 × f_o) + ∑(V₀₂/R_L) × duty factor LOW where:
f_i = input frequency in MHz;
f_o = output frequency in MHz;
∑ (C_L × V_CC2 × f_o) = sum of outputs;
C_L = output load capacitance in pF;
R_L = pull-up resistor in MΩ;
V_CC = supply voltage in Volts.
2. The condition is V_I = GND to V_CC − 1.5 V.
TYPICAL UNIT
16
ns
23
ns
56
MHz
3.5
pF
37
pF
1999 Oct 01
2