74HC86 Datasheet, PDF (2/6 Pages) NXP Semiconductors – Quad 2-input EXCLUSIVE-OR gate

Philips Semiconductors
Quad 2-input EXCLUSIVE-OR gate
Product specification
74HC/HCT86
FEATURES
• Output capability: standard
• I_CC category: SSI
GENERAL DESCRIPTION
The 74HC/HCT86 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT86 provide the EXCLUSIVE−OR function.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL PARAMETER
CONDITIONS
t_PHL/ t_PLH
C_I
C_PD
propagation delay nA, nB to nY
input capacitance
power dissipation capacitance per gate
C_L = 15 pF; V_CC = 5 V
notes 1 and 2
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + ∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz
f_o = output frequency in MHz
∑ (C_L × V_CC2 × f_o) = sum of outputs
C_L = output load capacitance in pF
V_CC = supply voltage in V
2. For HC the condition is V_I = GND to V_CC
For HCT the condition is V_I = GND to V_CC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
TYPICAL
HC
11
3.5
30
HCT
14
3.5
30
UNIT
ns
pF
pF
December 1990
2