74HC58 Datasheet, PDF (2/5 Pages) NXP Semiconductors – Dual AND-OR gate

Philips Semiconductors
Dual AND-OR gate
Product specification
74HC58
FEATURES
• Output capability: standard
• I_CC category: SSI
GENERAL DESCRIPTION
The 74HC58 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL).
It is specified in compliance with JEDEC standard no. 7A.
The “58” provides two sections of AND-OR gates. One section contains a 2-wide, 3-input (1A to 1F) AND-OR gate and
the second section contains a 2-wide, 2-input (2A to 2D) AND-OR gate.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 15 °C; t_r = t_f = 6 ns
SYMBOL
PARAMETER
t_PHL/ t_PLH
C_I
C_PD
Notes
propagation delay
1n to 1Y
2n to 2Y
input capacitance
power dissipation capacitance per
gate
CONDITIONS
C_L = 15 pF; V_CC = 5 V
notes 1 and 2
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + ∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz
f_o = output frequency in MHz
C_L = output load capacitance in pF
V_CC = supply voltage in V
∑ (C_L × V_CC2 × f_o) = sum of outputs
2. For HC the condition is V_I = GND to V_CC
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
TYPICAL
HC
11
9
3.5
18
UNIT
ns
ns
pF
pF
December 1990
2