74HC573 Datasheet, PDF (2/7 Pages) NXP Semiconductors – Octal D-type transparent latch; 3-state

Philips Semiconductors
Octal D-type transparent latch; 3-state
Product specification
74HC/HCT573
FEATURES
GENERAL DESCRIPTION
• Inputs and outputs on opposite
sides of package allowing easy
interface with microprocessors
• Useful as input or output port for
microprocessors/microcomputers
• 3-state non-inverting outputs for
bus oriented applications
• Common 3-state output enable
input
• Functionally identical to the “563”
and “373”
• Output capability: bus driver
• I_CC category: MSI
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
The 74HC/HCT573 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard no.
7A.
The 74HC/HCT573 are octal D-type
transparent latches featuring
separate D-type inputs for each latch
and 3-state outputs for bus oriented
applications.
A latch enable (LE) input and an
output enable (OE) input are common
to all latches.
The “573” consists of eight D-type
transparent latches with 3-state true
outputs. When LE is HIGH, data at
the D_n inputs enter the latches. In this
condition the latches are transparent,
i.e. a latch output will change state
each time its corresponding D-input
changes.
When LE is LOW the latches store the
information that was present at the
D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the
8 latches are available at the outputs.
When OE is HIGH, the outputs go to
the high impedance OFF-state.
Operation of the OE input does not
affect the state of the latches.
The “573” is functionally identical to
the “563” and “373”, but the “563” has
inverted outputs and the “373” has a
different pin arrangement.
SYMBOL
t_PHL/ t_PLH
C_I
C_PD
PARAMETER
CONDITIONS
propagation delay
D_n to Q_n
LE to Q_n
input capacitance
C_L = 15 pF; V_CC = 5 V
power dissipation capacitance per latch notes 1 and 2
TYPICAL
HC
HCT
14
17
15
15
3.5
3.5
26
26
UNIT
ns
ns
pF
pF
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i +∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz; f_o = output frequency in MHz
∑ (C_L × V_CC2 × f_o) = sum of outputs
C_L = output load capacitance in pF; V_CC = supply voltage in V
2. For HC the condition is V_I = GND to V_CC; for HCT the condition is V_I = GND to V_CC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
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