74HC564 Datasheet, PDF (2/7 Pages) NXP Semiconductors – Octal D-type flip-flop; positive-edge trigger; 3-state; inverting

Philips Semiconductors
Octal D-type flip-flop; positive-edge
trigger; 3-state; inverting
Product specification
74HC/HCT564
FEATURES
• 3-state inverting outputs for bus oriented applications
• 8-bit positive-edge triggered register
• Common 3-state output enable input
• Independent register and 3-state buffer operation
• Output capability: bus driver
• I_CC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT564 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT564 are octal D-type flip-flops featuring
separate D-type inputs for each flip-flop and inverting
3-state outputs for bus oriented applications. A clock (CP)
and an output enable (OE) input are common to all
flip-flops.
The 8 flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition.
When OE is LOW, the contents of the 8 flip-flops are
available at the outputs.
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
The “564” is functionally identical to the “574” but has
inverting outputs. The “564” is functionally identical to the
“534”, but has a different pinning.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL
t_PHL/ t_PLH
f_max
C_I
C_PD
PARAMETER
propagation delay CP to Q_n
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop
CONDITIONS
C_L = 15 pF; V_CC = 5 V
notes 1 and 2
TYPICAL
HC HCT
15 16
127 62
3.5 3.5
27 27
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i +∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz
f_o = output frequency in MHz
∑ (C_L × V_CC2 × f_o) = sum of outputs
C_L = output load capacitance in pF
V_CC = supply voltage in V
2. For HC the condition is V_I = GND to V_CC; for HCT the condition is V_I = GND to V_CC − 1.5 V
UNIT
ns
MHz
pF
pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2