74HC563N Datasheet, PDF (2/7 Pages) NXP Semiconductors – Octal D-type transparent latch 3-state inverting

Philips Semiconductors
Octal D-type transparent latch; 3-state;
inverting
Product specification
74HC/HCT563
FEATURES
• 3-state inverting outputs for bus
oriented applications
• Inputs and outputs on opposite
sides of package allowing easy
interface with microprocessor
• Common 3-state output enable
input
• Output capability: bus driver
• I_CC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT563 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard no.
7A.
The 74HC/HCT563 are octal D-type
transparent latches featuring
separate D-type inputs for each latch
and inverting 3-state outputs for bus
oriented applications.
A latch enable (LE) input and an
output enable (OE) input are common
to all latches.
The “563” is functionally identical to
the “573”, but has inverted outputs.
The “563” consists of eight D-type
transparent latches with 3-state
inverting outputs. The LE and OE are
common to all latches.
When LE is HIGH, data at the D_n
inputs enter the latches. In this
condition the latches are transparent,
i.e. a latch output will change state
each time its corresponding D-input
changes.
When LE is LOW the latches store the
information that was present at the
D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the
8 latches are available at the outputs.
When OE is HIGH, the outputs go to
the high impedance OFF-state.
Operation of the OE input does not
affect the state of the latches.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL PARAMETER
CONDITIONS
t_PHL/ t_PLH
C_I
C_PD
propagation delay D_n, LE to Q_n
input capacitance
power dissipation capacitance per latch
C_L = 15 pF; V_CC = 5 V
notes 1 and 2
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + ∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz
f_o = output frequency in MHz
∑ (C_L × V_CC2 × f_o) = sum of outputs
C_L = output load capacitance in pF
V_CC = supply voltage in V
2. For HC the condition is V_I = GND to V_CC
for HCT the condition is V_I = GND to V_CC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
TYPICAL
HC
HCT
14
16
3.5
3.5
19
19
UNIT
ns
pF
pF
December 1990
2