74HC4353 Datasheet, PDF (2/16 Pages) NXP Semiconductors – Triple 2-channel analog multiplexer/demultiplexer with latch

Philips Semiconductors
Triple 2-channel analog
multiplexer/demultiplexer with latch
Product specification
74HC/HCT4353
FEATURES
• Wide analog input voltage range: ± 5 V
• Low “ON” resistance:
80 Ω (typ.) at V_CC − V_EE = 4.5 V
70 Ω (typ.) at V_CC − V_EE = 6.0 V
60 Ω (typ.) at V_CC − V_EE = 9.0 V
• Logic level translation:
to enable 5 V logic to communicate with ± 5 V analog
signals
• Typical “break before make” built in
• Address latches provided
• Output capability: non-standard
• I_CC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4353 are high-speed Si-gate CMOS
devices. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT4353 are triple 2-channel analog
multiplexers/demultiplexers with two common enable
inputs (E₁ and E₂) and a latch enable input (LE). Each
multiplexer has two independent inputs/outputs (nY₀ and
nY₁), a common input/output (nZ) and select inputs (S₁ to
S₃).
Each multiplexer/demultiplexer contains two bidirectional
analog switches, each with one side connected to an
independent input/output (nY₀ and nY₁) and the other side
connected to a common input/output (nZ).
With E₁ LOW and E₂ HIGH, one of the two switches is
selected (low impedance ON-state) by S₁ to S₃.
The data at the select inputs may be latched by using the
active LOW latch enable input (LE). When LE is HIGH, the
latch is transparent. When either of the two enable inputs,
E₁ (active LOW) and E₂ (active HIGH), is inactive, all
analog switches are turned off.
V_CC and GND are the supply voltage pins for the digital
control inputs (S₁ to S₃, LE, E₁ and E₂). The V_CC to GND
ranges are 2.0 to 10.0 V for HC and 4.5 to 5.5 V for HCT.
The analog inputs/outputs (nY₀ and nY₁, and nZ) can
swing between V_CC as a positive limit and V_EE as a
negative limit. V_CC − V_EE may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, V_EE is
connected to GND (typically ground).
QUICK REFERENCE DATA
V_EE = GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL
PARAMETER
t_PZH/ t_PZL
t_PHZ/ t_PLZ
C_I
C_PD
C_S
turn “ON” time E₁, E₂ or S_n to V_os
turn “OFF” time E₁, E₂ or S_n to V_os
input capacitance
power dissipation capacitance per switch
max. switch capacitance
independent (Y)
common (Z)
Notes
1. C_PD is used to determine the dynamic power
dissipation (P_D in µW):
P_D =
C_PD × V_CC2 × f_i + ∑ {(C_L + C_S) × V_CC2 × f_o} where:
f_i = input frequency in MHz
C_L = output load capacitance in pF
f_o = output frequency in MHz
C_S = max. switch capacitance in pF
CONDITIONS
C_L = 50 pF; R_L = 1 kΩ;
V_CC = 5 V
notes 1 and 2
TYPICAL
HC
29
20
3.5
23
HCT
21
22
3.5
23
UNIT
ns
ns
pF
pF
5
5
pF
8
8
pF
∑ {(C_L ×C_S) × V_CC2 × f_o} = sum of outputs
V_CC = supply voltage in V
2. For HC the condition is V_I = GND to V_CC
For HCT the condition is V_I = GND to V_CC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package
Information”.
December 1990
2