74HC4066 Datasheet, PDF (2/24 Pages) NXP Semiconductors – Quad bilateral switches

Philips Semiconductors
Quad bilateral switches
Product specification
74HC/HCT4066
FEATURES
• Very low “ON” resistance:
50 Ω (typ.) at V_CC = 4.5 V
45 Ω (typ.) at V_CC = 6.0 V
35 Ω (typ.) at V_CC = 9.0 V
• Output capability: non-standard
• I_CC category: SSI.
The 74HC/HCT4066 have four independent analog
switches. Each switch has two input/output terminals (nY,
nZ) and an active HIGH enable input (nE). When nE is
LOW the belonging analog switch is turned off.
The “4066” is pin compatible with the “4016” but exhibits a
much lower “ON” resistance. In addition, the “ON”
resistance is relatively constant over the full input signal
range.
GENERAL DESCRIPTION
The 74HC/HCT4066 are high-speed Si-gate CMOS
devices and are pin compatible with the “4066” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL
t_PZH/ t_PZL
t_PHZ/ t_PLZ
C_I
C_PD
C_S
PARAMETER
turn-on time nE to V_os
turn-off time nE to V_os
input capacitance
power dissipation capacitance per switch
max. switch capacitance
CONDITIONS
TYPICAL
UNIT
HC HCT
C_L = 15 pF; R_L = 1 kΩ; V_CC = 5 V 11 12 ns
13 16 ns
3.5 3.5 pF
notes 1 and 2
11 12 pF
8
8
pF
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
a) P_D = C_PD × V_CC2 × f_i + ∑ {(C_L + C_S) × V_CC2 × f_o} where:
b) f_i = input frequency in MHz
c) f_o = output frequency in MHz
d) ∑ {(C_L + C_S) × V_CC2 × f_o} = sum of outputs
e) C_L = output load capacitance in pF
f) C_S = maximum switch capacitance in pF
g) V_CC = supply voltage in V
2. For HC the condition is V_I = GND to V_CC
For HCT the condition is V_I = GND to V_CC − 1.5 V
1998 Nov 10
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