74HC4050 Datasheet, PDF (2/7 Pages) NXP Semiconductors – Hex high-to-low level shifter

Philips Semiconductors
Hex high-to-low level shifter
Product specification
74HC4050
FEATURES
• Output capability: standard
• I_CC category: SSI
GENERAL DESCRIPTION
The 74HC4050 is a high-speed Si-gate CMOS device and
is pin compatible with the “4050” of the “4000B” series. It
is specified in compliance with JEDEC standard no. 7A.
The 74HC4050 provides six non-inverting buffers with a
modified input protection structure, which has no diode
connected to V_CC. Input voltages of up to 15 V may
therefore be used. This feature enables the non-inverting
buffers to be used as logic level translators, which will
convert high level logic to low level logic, while operating
from a low voltage power supply. For example 15 V logic
(“4000B series”) can be converted down to 2 V logic.
The actual input switch level remains related to the V_CC
and is the same as mentioned in the family characteristics.
APPLICATIONS
• Converting 15 V logic (“4000B” series) down to 2 V logic.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL
PARAMETER
t_PHL / t_PLH
C_I
C_PD
Notes
propagation delay nA to nY
input capacitance
power dissipation capacitance per buffer
CONDITIONS
C_L = 15 pF; V_CC = 5 V
note 1
TYPICAL
HC
7
3.5
14
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i +∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz
f_o = output frequency in MHz
C_L = output load capacitance in pF
V_CC = supply voltage in V
∑ (C_L × V_CC2 × f_o) = sum of outputs
UNIT
ns
pF
pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2