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74HC3G07 Datasheet, PDF (2/14 Pages) NXP Semiconductors – Buffer with open-drain outputs | |||
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Philips Semiconductors
Buffer with open-drain outputs
Product speciï¬cation
74HC3G07; 74HCT3G07
FEATURES
⢠Wide supply voltage range from 2.0 to 6.0 V
⢠High noise immunity
⢠Low power dissipation
⢠ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
⢠Multiple package options
⢠Specified from â40 to +85 °C and â40 to +125 °C.
DESCRIPTION
The 74HC3G/HCT3G07 is a high-speed Si-gate CMOS
device. Specified in compliance with JEDEC standard
no. 7A.
The 74HC3G/HCT3G07 provides three non-inverting
buffers.
The outputs of the 74HC3G/HCT3G07 devices are open
drains and can be connected to other open-drain outputs
to implement active-LOW, wired-OR or active-HIGH
wired-AND functions. For digital operation this device must
have a pull-up resistor to establish a logic HIGH-level.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ⤠6.0 ns.
SYMBOL
PARAMETER
CONDITIONS
tPZL
propagation delay nA to nY
tPLZ
propagation delay nA to nY
CI
input capacitance
CPD
power dissipation capacitance
CL = 50 pF; VCC = 4.5 V
CL = 50 pF; VCC = 4.5 V
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD à VCC2 à fi à N + â (CL à VCC2 à fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
â (CL Ã VCC2 Ã fo) = sum of outputs.
2. For 74HC3G07 the condition is VI = GND to VCC.
For 74HCT3G07 the condition is VI = GND to VCC â 1.5 V.
TYPICAL
HC3G
9
11
1.5
4
HCT3G
11
10
1.5
4
UNIT
ns
ns
pF
pF
2003 Oct 15
2
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