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74HC377 Datasheet, PDF (2/7 Pages) NXP Semiconductors – Octal D-type flip-flop with data enable; positive-edge trigger | |||
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Philips Semiconductors
Octal D-type ï¬ip-ï¬op with data enable;
positive-edge trigger
Product speciï¬cation
74HC/HCT377
FEATURES
⢠Ideal for addressable register applications
⢠Data enable for address and data synchronization
applications
⢠Eight positive-edge triggered D-type flip-flops
⢠See â273â for master reset version
⢠See â373â for transparent latch version
⢠See â374â for 3-state version
⢠Output capability: standard
⢠ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT377 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT377 have eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs. A common
clock (CP) input loads all flip-flops simultaneously when
the data enable (E) is LOW. The state of each D input, one
set-up time before the LOW-to-HIGH clock transition, is
transferred to the corresponding output (Qn) of the flip-flop.
The E input must be stable only one set-up time prior to the
LOW-to-HIGH transition for predictable operation.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/ tPLH
fmax
CI
CPD
propagation delay CP to Qn
maximum clock frequency
input capacitance
power dissipation capacitance per ï¬ip-ï¬op
CL = 15 pF; VCC = 5 V
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD Ã VCC2 Ã fi + â (CL Ã VCC2 Ã fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
â (CL Ã VCC2 Ã fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC â 1.5 V
ORDERING INFORMATION
See â74HC/HCT/HCU/HCMOS Logic Package Informationâ.
TYPICAL
UNIT
HC HCT
13 14 ns
77 53 MHz
3.5 3.5 pF
20 20 pF
December 1990
2
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