74HC366 Datasheet, PDF (2/7 Pages) NXP Semiconductors – Hex buffer/line driver; 3-state; inverting

Philips Semiconductors
Hex buffer/line driver; 3-state; inverting
Product specification
74HC/HCT366
FEATURES
• Inverting outputs
• Output capability: bus driver
• I_CC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT366 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT366 are hex inverting buffer/line drivers
with 3-state outputs. The 3-state outputs (nY) are
controlled by the output enable inputs (OE₁, OE₂).
A HIGH on OE_n causes the outputs to assume a high
impedance OFF-state.
The ”366” is identical to the “365” but has inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL
PARAMETER
CONDITIONS
t_PHL/ t_PLH
C_I
C_PD
propagation delay
nA to nY
input capacitance
power dissipation capacitance per buffer
C_L = 15 pF; V_CC = 5 V
notes 1 and 2
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + ∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz
f_o = output frequency in MHz
∑ (C_L × V_CC2 × f_o) = sum of outputs
C_L = output load capacitance in pF
V_CC = supply voltage in V
2. For HC the condition is V_I = GND to V_CC
For HCT the condition is V_I = GND to V_CC − 1.5 V
TYPICAL
HC
10
HCT
11
UNIT
ns
3.5
3.5
pF
30
30
pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2