74HC299 Datasheet, PDF (2/11 Pages) NXP Semiconductors – 8-bit universal shift register; 3-state

Philips Semiconductors
8-bit universal shift register; 3-state
Product specification
74HC/HCT299
FEATURES
• Multiplexed inputs/outputs provide improved bit density
• Four operating modes:
– shift left
– shift right
– hold (store)
– load data
• Operates with output enable or at high-impedance
OFF-state (Z)
• 3-state outputs drive bus lines directly
• Can be cascaded for n-bits word length
• Output capability: bus driver (parallel I/Os),
standard (serial outputs)
• I_CC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT299 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT299 contain eight edge-triggered D-type
flip-flops and the interstage logic necessary to perform
synchronous shift-right, shift-left, parallel load and hold
operations. The type of operation is determined by the
mode select inputs (S₀ and S₁), as shown in the mode
select table.
All flip-flop outputs have 3-state buffers to separate these
outputs (I/O₀ to I/O₇) such, that they can serve as data
inputs in the parallel load mode. The serial outputs (Q₀ and
Q₇) are used for expansion in serial shifting of longer
words.
A LOW signal on the asynchronous master reset input
(MR) overrides the S_n and clock (CP) inputs and resets the
flip-flops. All other state changes are initiated by the rising
edge of the clock pulse. Inputs can change when the clock
is either state, provided that the recommended set-up and
hold times, relative to the rising edge of CP, are observed.
A HIGH signal on the 3-state output enable inputs (OE₁ or
OE₂) disables the 3-state buffers and the I/O_n outputs are
set to the high-impedance OFF-state. In this condition, the
shift, hold, load and reset operations can still occur. The
3-state buffers are also disabled by HIGH signals on both
S₀ and S₁, when in preparation for a parallel load
operation.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL PARAMETER
t_PHL/ t_PLH
t_PHL
f_max
C_I
C_I/O
C_PD
propagation delay
CP to Q₀, Q₇
CP to I/O_n
MR to Q₀, Q₇ or I/O_n
maximum clock frequency
input capacitance
input/output capacitance
power dissipation capacitance per package
Notes
1. C_PD is used to determine the dynamic power
dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + ∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz
f_o = output frequency in MHz
∑ (C_L × V_CC2 × f_o) = sum of outputs
C_L = output load capacitance in pF
V_CC = supply voltage in V
CONDITIONS
C_L = 15 pF; V_CC = 5 V
notes 1 and 2
TYPICAL
UNIT
HC HCT
20 19 ns
20 19 ns
20 23 ns
50 46 MHz
3.5 3.5 pF
10 10 pF
120 125 pF
2. For HC the condition is V_I = GND to V_CC
For HCT the condition is V_I = GND to V_CC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package
Information”.
December 1990
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