74HC242 Datasheet, PDF (2/7 Pages) NXP Semiconductors – Quad bus transceiver; 3-state; inverting

Philips Semiconductors
Quad bus transceiver; 3-state; inverting
Product specification
74HC/HCT242
FEATURES
• Inverting 3-state outputs
• 2-way asynchronous data bus communication
• Output capability: bus driver
• I_CC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT242 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT242 are quad bus transceivers featuring
inverting 3-state bus compatible outputs in both send and
receive directions.
They are designed for 4-line asynchronous 2-way data
communications between data buses.
The output enable inputs (OE_A and OE_B) can be used to
isolate the buses.
The “242” is similar to the “243” but has inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL
PARAMETER
CONDITIONS
t_PHL/ t_PLH
C_I
C_I/O
C_PD
propagation delay
A_n to B_n;
B_n to A_n
input capacitance
input/output capacitance
power dissipation capacitance per transceiver
C_L = 15 pF; V_CC = 5 V
notes 1 and 2
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + ∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz
f_o = output frequency in MHz
∑ (C_L × V_CC2 × f_o) = sum of outputs
C_L = output load capacitance in pF
V_CC = supply voltage in V
2. For HC the condition is V_I = GND to V_CC
For HCT the condition is V_I = GND to V_CC − 1.5 V
TYPICAL
HC
7
HCT
10
3.5
3.5
10
10
29
32
UNIT
ns
pF
pF
pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2