74HC157 Datasheet, PDF (2/7 Pages) NXP Semiconductors – Quad 2-input multiplexer

Philips Semiconductors
Quad 2-input multiplexer
Product specification
74HC/HCT157
FEATURES
• Non-inverting data path
• Output capability: standard
• I_CC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT157 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT157 are quad 2-input multiplexers which
select 4 bits of data from two sources under the control of
a common data select input (S). The four outputs present
the selected data in the true (non-inverted) form. The
enable input (E) is active LOW. When E is HIGH, all of the
outputs (1Y to 4Y) are forced LOW regardless of all other
input conditions.
Moving the data from two groups of registers to four
common output buses is a common use of the “157”. The
state of the common data select input (S) determines the
particular register from which the data comes. It can also
be used as function generator.
The device is useful for implementing highly irregular logic
by generating any four of the 16 different functions of two
variables with one variable common.
The “157” is the logic implementation of a 4-pole,
2-position switch, where the position of the switch is
determined by the logic levels applied to S.
The logic equations are:
1Y = E.(1l₁.S + 1l₀.S)
2Y = E.(2l₁.S + 2l₀.S)
3Y = E.(3l₁.S + 3l₀.S)
4Y = E.(4l₁.S + 4l₀.S)
The “157” is identical to the “158” but has non-inverting
(true) outputs.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL
t_PHL/ t_PLH
C_I
C_PD
PARAMETER
CONDITIONS
propagation delay
nI₀, nI₁ to nY
E to nY
C_L = 15 pF; V_CC = 5 V
S to nY
input capacitance
power dissipation capacitance per multiplexer notes 1 and 2
TYPICAL
HC HCT
11 13
11 12
12 19
3.5 3.5
70 70
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + ∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz
f_o = output frequency in MHz
∑ (C_L × V_CC2 × f_o) = sum of outputs
C_L = output load capacitance in pF
V_CC = supply voltage in V
2. For HC the condition is V_I = GND to V_CC
For HCT the condition is V_I = GND to V_CC − 1.5 V
UNIT
ns
ns
ns
pF
pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2