74HC154 Datasheet, PDF (2/7 Pages) NXP Semiconductors – 4-to-16 line decoder/demultiplexer

Philips Semiconductors
4-to-16 line decoder/demultiplexer
Product specification
74HC/HCT154
FEATURES
• 16-line demultiplexing capability
• Decodes 4 binary-coded inputs into one of 16 mutually
exclusive outputs
• 2-input enable gate for strobing or expansion
• Output capability: standard
• I_CC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT154 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT154 decoders accept four active HIGH
binary address inputs and provide 16 mutually exclusive
active LOW outputs.
The 2-input enable gate can be used to strobe the decoder
to eliminate the normal decoding “glitches” on the outputs,
or it can be used for the expansion of the decoder.
The enable gate has two AND’ed inputs which must be
LOW to enable the outputs.
The “154” can be used as a 1-to-16 demultiplexer by using
one of the enable inputs as the multiplexed data input.
When the other enable is LOW, the addressed output will
follow the state of the applied data.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL PARAMETER
CONDITIONS
t_PHL/ t_PLH
C_I
C_PD
propagation delay A_n, E_n to Y_n
input capacitance
power dissipation capacitance per package
C_L = 15 pF; V_CC = 5 V
notes 1 and 2
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + ∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz
f_o = output frequency in MHz
∑ (C_L × V_CC2 × f_o) = sum of outputs
C_L = output load capacitance in pF
V_CC = supply voltage in V
2. For HC the condition is V_I = GND to V_CC
For HCT the condition is V_I = GND to V_CC − 1.5 V
TYPICAL
HC
HCT
11
13
3.5
3.5
60
60
UNIT
ns
pF
pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
September 1993
2