74F786 Datasheet, PDF (2/12 Pages) NXP Semiconductors – 4-bit asynchronous bus arbiter

Philips Semiconductors
4-bit asynchronous bus arbiter
Product specification
74F786
FEATURES
• Arbitrates between 4 asynchronous inputs
• Separate grant output for each input
• Common output enable
• On board 4 input AND gate
• Metastable–free outputs
• Industrial temperature range available (–40°C to +85°C)
The 74F786 is designed so that contention between two or more
request signals will not glitch or display a metastable condition. In
this situation an increase in the BRn to BGn t_PHL may be observed.
A typical 74F786 has an h = 6.6ns, t = 0.41ns and To = 5µsec.
Where:
h = Typical propagation delay through the device and t and To are
device parameters derived from test results and can most nearly be
defined as:
t = A function of the rate at which a latch in a metastable state
resolves that condition.
DESCRIPTION
The 74F786 is an asynchronous 4–bit arbiter designed for high
speed real–time applications. The priority of arbitration is determined
on a first–come first–served basis. Separate bus grant (BGn)
outputs are available to indicate which one of the request inputs is
served by the arbitration logic. All BGn outputs are enabled by a
common enable (EN) pin. In order to generate a bus request signal
a separate 4 input AND gate is provided which may also be used as
an independent AND gate. Unused bus request (BR) inputs may be
disabled by tying them high.
To = A function of the measurement of the propensity of a latch to
enter a metastable state. To is also a very strong function of the
normal propagation delay of the device.
For further information, please refer to the 74F786 application notes.
TYPE
74F786
TYPICAL
PROPAGATION DELAY
6.6ns
TYPICAL
SUPPLY CURRENT
(TOTAL)
55mA
ORDERING INFORMATION
DESCRIPTION
16–pin plastic DIP
16–pin plastic SO
COMMERCIAL RANGE
V_CC = 5V ±10%,
T_amb = 0°C to +70°C
N74F786N
N74F786D
ORDER CODE
INDUSTRIAL RANGE
V_CC = 5V ±10%,
T_amb = –40°C to +85°C
I74F786N
I74F786D
PKG DWG #
SOT 38-4
SOT109-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/
LOW
BR0 – BR3
Bus request inputs (active low)
A, B, C, D
AND gate inputs
EN
Common bus grant output enable input (active low)
YOUT
AND gate output
BG0 – BG3
Bus grant outputs (active low)
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
1.0/3.0
1.0/1.0
1.0/1.0
150/40
150/40
LOGIC SYMBOL
IEC/IEEE SYMBOL
LOAD VALUE HIGH/
LOW
20µA/1.8mA
20µA/0.6mA
20µA/0.6mA
3.0mA/24mA
3.0mA/24mA
4 5 6 7 15 1 2 3
BR0 BR1 BR2 BR3 A B C D
6
EN
BG0 BG1 BG2 BG3 YOUT
V_CC = Pin 16
GND = Pin 8
13 12 11 10 14
SF00442
BUS ARBITER
Φ
9
74F786
EN
4
BR0
5
BR1
6
BR2
7
BR3
BG0
13
BG1
12
BG2
11
BG3
10
15
&
1
2
14
3
SF00443
February 14, 1991
2
853–1269 01717