74F670 Datasheet, PDF (2/12 Pages) NXP Semiconductors – 4 x 4 register file 3-State

Philips Semiconductors
4 x 4 register file (3-State)
Product specification
74F670
FEATURES
• Simultaneous and Independent Read and Write operations
• Expandable to almost any word size and bit length
• 3-State outputs
DESCRIPTION
The 74F670 is a 16-bit 3-State Register File organized as 4 words of
4 bits each. Separate Read and Write Address and Enable inputs
are available, permitting simultaneous writing into one word location
and reading from another location. The 4-bit word to be stored is
presented to four data inputs.
The Write address inputs (WA and WB) determine the location of the
stored word. The Write Address inputs should only be changed
when the Write Enable input (WE) is High for conventional
operation. When the WE is Low, the data is entered into the
addressed location.
The addressed location remains transparent to the data while the
WE is Low. Data supplied at the inputs will be read out in true
(non-inverting) form from the 3-State outputs. Data and address
inputs are inhibited when the WE is High. Direct acquisition of data
stored in any of the four registers is made possible by individual
Read Address inputs (RA, RB). The addressed word appears at the
four outputs when the Read Enable (RE) is Low. Data outputs are in
the high impedance “off” state when the RE is High. This permits
outputs to be tied together to increase the word capacity to very
large numbers.
Up to 128 devices can be stacked to increase the word size to 512
locations by tying the 3-State outputs together. Since the limiting
factor for expansion is the output High current, further stacking is
possible by tying pullup reisistors to the outputs to increase the I_OH
current available. Design of the Read Enable signals for the stacked
devices must ensure that there is no overlap in the Low levels which
cause more than one output to be active at the same time. Parallel
expansion to generate n-bit words is accomplished by driving the
Enable and address inputs of each device in parallel.
PIN CONFIGURATION
D1 1
D2 ²
D3 ³
RB 4
RA 5
Q3 6
Q2 7
GND 8
16 V_CC
15 D0
14 WA
13 WB
12 WE
11 RE
10 Q0
9 Q1
SF01178
TYPE
74F670
TYPICAL
PROPAGATION
DELAY
6.5ns
TYPICAL
SUPPLY CURRENT
(TOTAL)
50mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
V_CC = 5V ±10%,
T_amb = 0°C to +70°C
16-pin plastic DIP
N74F670N
16-pin plastic SOL
N74F670D
PKG DWG #
SOT38-4
SOT162-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
D0 - D3
Data inputs
1.0/1.0
WA, WB
Write address inputs
1.0/1.0
RA, RB
Read address inputs
1.0/1.0
WE
Write Enable inputs
1.0/1.0
RE
Read Enable inputs
1.0/1.0
Q0–Q3
Data output
150/40
NOTE:
One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20mA/0.6mA
20mA/0.6mA
3.0mA/24mA
1990 Jul 12
2
853-0014 99965