74F597 Datasheet, PDF (2/12 Pages) NXP Semiconductors – 8-bit shift register with input storage registers

Philips Semiconductors
8-bit shift register with input storage registers
Product specification
74F597
FEATURES
• High impedance PNP base inputs for reduced loading
(20µA in High and Low states)
• 8-bit parallel storage register
• 3-State output buffers
• Shift register has asynchronous direct overriding reset
• Shift load SHLD is functional when SHCP is Low and locked out
when SHCP is High
• Guaranteed shift frequency DC to 105MHz
PIN CONFIGURATION
D1 1
D2 2
D3 3
D4 4
D5 5
D6 6
D7 7
GND 8
16 V_CC
15 D0
14 D_S
13 SHLD
12 STCP
11 SHCP
10 SHRST
9 Q_S
DESCRIPTION
The 74F597 consists of an 8-bit storage register feeding a
parallel-in/serial-in, serial-out 8-bit shift register. The storage register
and shift register have separate positive edge triggered clocks. The
shift register has asynchronous reset and when SHCP is Low, it has
asynchronous load.
The shift register load function has been modified to load when both
SHLD and SHCP are Low. When SHCP is High the shift register
load operation is not performed. Data will be properly shifted on the
rising edge of SHCP when SHLD is High.
SF00366
TYPE
74F597
TYPICAL f_MAX
135MHz
TYPICAL SUPPLY CURRENT
(TOTAL)
42mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
V_CC = 5V ±10%,
T_amb = 0°C to +70°C
16-pin plastic DIP
N74F597N
16-pin plastic SO
N74F597D
PKG DWG #
SOT38-4
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
Ds
Serial data input
D0–D7
Parallel data inputs
SHCP
Shift register clock pulse input
STCP
Storage register clock pulse input
SHLD
Shift register load input (active Low)
SHRST
Shift register reset input (active Low)
Qs
Serial data output
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
74F (U.L.)
HIGH/LOW
1.0/0.033
1.0/0.033
1.0/0.033
1.0/0.033
1.0/0.033
1.0/0.033
50/33
LOAD VALUE
HIGH/LOW
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
1.0mA/20mA
1991 Sep 13
2
853–1556 03964