74F280B Datasheet, PDF (2/8 Pages) NXP Semiconductors – 9-bit odd/even parity generator/checker

Philips Semiconductors
9-bit odd/even parity generator/checker
Product specification
74F280B
FEATURES
• High-impedance NPN base inputs for reduced loading
(20µA in Low and High states)
• Buffered inputs — one normalized load
• Word length easily expanded by cascading
• Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F280B is a 9-bit Parity Generator or Checker commonly used
to detect errors in high speed data transmission or data retrieval
systems. Both Even (∑_E) and Odd (∑_O) parity outputs are available
for generating or checking even or odd parity on up to 9 bits.
The Even (∑_E) parity output is High when an even number of Data
inputs (I₀ - I₈) are High. The Odd (∑_O) parity output is High when an
odd number of Data inputs are High.
Expansion to larger word sizes is accomplished by tying the Even
(∑_E) outputs of up to nine parallel devices to the data inputs of the
final stage. This expansion scheme allows an 81-bit data word to be
checked in less than 20ns.
ORDERING INFORMATION
DESCRIPTION
14-pin plastic DIP
14-pin plastic SO
COMMERCIAL RANGE
V_CC = 5V ±10%,
T_amb = 0°C to +70°C
N74F280BN
N74F280BD
PIN CONFIGURATION
I₆ 1
I₇ 2
NC 3
I₈ 4
Σ_E 5
Σ_O 6
GND 7
14 V_CC
13 I₅
12 I₄
11 I₃
10 I₂
9 I₁
8 I₀
SF00849
TYPE
74F280B
TYPICAL
PROPAGATION
DELAY
5.5ns
TYPICAL
SUPPLY CURRENT
(TOTAL)
26mA
INDUSTRIAL RANGE
V_CC = 5V ±10%,
T_amb = –40°C to +85°C
I74F280BN
I74F280BD
PKG. DWG. #
SOT27-1
SOT108-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
I₀ - I₈
Data inputs
1.0/0.033
∑_E, ∑_O
Parity outputs
50/33
NOTE:
One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
IEC/IEEE SYMBOL
LOAD VALUE
HIGH/LOW
20µA/20µA
1.0mA/20mA
8 9 10 11 12 13 1 2 4
I₀ I₁ I₂ I₃ I₄ I₅ I₆ I₇ I₈
Σ_E
Σ_O
5
6
SF00845
8
2K
9
10
11
Σ_E
5
12
13
1
Σ_O
6
2
4
V_CC=Pin 14
GND=Pin 7
SF00846
1996 Mar 12
2
853-0363 16555