74F256 Datasheet, PDF (2/12 Pages) NXP Semiconductors – Dual addressable latch

Philips Semiconductors
Dual addressable latch
Product specification
74F256
FEATURES
• Combines dual demultiplexer and 8-bit latch
• Serial-to-parallel capability
• Output from each storage bit available
• Random (addressable) data entry
• Easily expandable
• Common reset input
• Useful as dual 1-of-4 active High decoder
PIN CONFIGURATION
A0 1
A1 2
Da 3
Q0a 4
Q1a 5
Q2a 6
Q3a 7
GND 8
16 _VCC
15 _MR
14 _E
13 _Db
12 _Q3b
11 Q2b
10 Q1b
9 Q0b
DESCRIPTION
The 74F256 dual addressable latch has four distinct modes of
operation which are selectable by controlling the Master Reset (MR)
and Enable (E) inputs (see Function Table). In the addressable latch
mode, data at the Data inputs is written into the addressed latches.
The addressed latches will follow the Data input with all
unaddressed latches remaining in their previous states. In the
memory mode, all latches remain in their previous states and are
unaffected by the Data or Address inputs. To eliminate the possibility
of entering erroneous data in the latches, the enable should be held
High (inactive) while the address lines are changing. In the dual
1-of-4 decoding or demultiplexing mode (MR=E=Low), addressed
outputs will follow the level of the Data inputs, with all other outputs
Low. In the Master Reset mode, all outputs are Low and unaffected
by the Address and Data inputs.
SF00805
TYPE
74F256
TYPICAL
PROPAGATION
DELAY
7.0ns
TYPICAL SUPPLY
CURRENT (TOTAL)
28mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
16-pin plastic DIP
COMMERCIAL RANGE
V_CC = 5V ±10%,
T_amb = 0°C to +70°C
N74F256N
16-pin plastic SO
N74F256D
PKG DWG #
SOT38-4
SOT109-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
Da, Db
Port A, port B inputs
A0, A1
Address inputs
E
Enable (active Low)
MR
Master Reset inputs (active Low)
Q0a – Q3a
Port A outputs
Q0b – Q3b
Port B outputs
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
74F (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33
50/33
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
1.0mA/20mA
1.0mA/20mA
1988 Nov 29
2
853–0359 95207