74F195A Datasheet, PDF (2/10 Pages) NXP Semiconductors – 4-bit parallel-access shift register

Philips Semiconductors
4-bit parallel-access shift register
Product specification
74F195A
FEATURES
• Shift right and parallel load capability
• J – K (D) inputs to first stage
• Complement output from last stage
• Asynchronous Master Reset
• Diode inputs
DESCRIPTION
The 74F195A is a 4-Bit Parallel Access Shift Register and its
functional characteristics are indicated in the Logic Diagram and
Function Table. This device is useful in a variety of shifting, counting
and storage applications. It performs serial, parallel, serial to
parallel, or parallel to serial data transfers at very high speeds.
The 74F195A operates in two primary modes: shift right (Q0→Q1)
and parallel load, which are controlled by the state of the Parallel
Enable (PE) input. Serial data enters the first flip-flop (Q0) via the J
and K inputs when the PE input is High, and is shifted one bit in the
direction Q0→Q1→Q2→Q3 following each Low-to-High clock
transition.
The J and K inputs provide the flexibility of the J-K type input for
special applications, and by tying the two together the simple D-type
input is made for general applications.
The device appears as four common clocked D flip-flops when the
PE input is Low. After the Low-to-High clock transition, data on the
parallel inputs (D0–D3) is transferred to the respective Q0–Q3
outputs. Shift left operation (Q3–Q2) can be achieved by tying the
Qn outputs to the Dn-1 inputs and holding the PE input Low.
All parallel and serial data transfers are synchronous, occurring after
each Low-to-High clock transition. The 74F195A utilizes
edge-triggering, therefore there is no restriction on the activity of the
J, K, Dn, and PE inputs for logic operation, other than the set-up and
hold time requirements.
A Low on the asynchronous Master Reset (MR) input sets all Q
outputs Low, independent of any other input condition.
PIN CONFIGURATION
MR 1
J2
K3
D0 4
D1 5
D2 6
D3 7
GND 8
16 V_CC
15 Q0
14 Q1
13 Q2
12 Q3
11 _Q3
10 _CP
9 PE
SF00757
TYPE
74F195A
TYPICAL f_MAX
180MHz
TYPICAL
SUPPLY CURRENT
(TOTAL)
40mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
V_CC = 5V ±10%,
T_amb = 0°C to +70°C
16-pin plastic DIP
N74F195AN
16-pin plastic SO
N74F195AD
PKG. DWG. #
SOT 38-4
SOT 109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
D0–D3
Data inputs
74F195
74F195A
J, K
J-K or D type serial inputs
74F195
74F195A
CP
Clock Pulse input (active rising edge)
74F195
74F195A
MR
Master Reset input (active Low)
74F195
74F195A
Q0–Q3,
Q3
Data outputs
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
74F (U.L.)
HIGH/LOW
1.0/0.033
1.0/1.0
1.0/0.033
1.0/1.0
1.0/0.033
1.0/1.0
2.0/0.066
1.0/1.0
50/33
LOAD VALUE HIGH/LOW
20µA/20µA
20µA/0.6mA
20µA/20µA
20µA/0.6mA
20µA/20µA
20µA/0.6mA
40µA/40µA
20µA/0.6mA
1.0mA/20mA
1996 Mar 12
2
853-0024 16555