74ALVCH16501 Datasheet, PDF (2/13 Pages) NXP Semiconductors – 18-bit universal bus transceiver 3-State

Philips Semiconductors
18-bit universal bus transceiver (3-State)
Product specification
74ALVCH16501
FEATURES
• Complies with JEDEC standard no. 8-1A.
• CMOS low power consumption
• Direct interface with TTL levels
• Current drive ± 24 mA at 3.0 V
• Universal bus transceiver with D-type latches and D-type flip-flops
capable of operating in transparent, latched or clocked mode.
• All inputs have bushold circuitry
• Output drive capability 50Ω transmission lines @ 85°C
• 3-State non-inverting outputs for bus oriented applications
DESCRIPTION
The 74ALVCH16501 is an 18-bit universal transceiver featuring
non-inverting 3-State bus compatible outputs in both send and
receive directions. Data flow in each direction is controlled by output
enable (OE_AB and OE_BA), latch enable (LE_AB and LE_BA), and clock
(CP_AB and CP_BA) inputs. For A-to-B data flow, the device operates
in the transparent mode when LE_AB is High. When LE_AB is Low, the
A data is latched if CP_AB is held at a High or Low logic level. If LE_AB
is Low, the A-bus data is stored in the latch/flip-flop on the
Low-to-High transition of CP_AB. When OE_AB is High, the outputs are
active. When OE_AB is Low, the outputs are in the high-impedance
state.
Data flow for B-to-A is similar to that of A-to-B but uses OE_BA, LE_BA
and CP_BA. The output enables are complimentary (OE_AB is active
High, and OE_BA is active Low).
To ensure the high impedance state during power up or power
down, OE_BA should be tied to V_CC through a pullup resistor and
OE_AB should be tied to GND through a pulldown resistor; the
minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
QUICK REFERENCE DATA
GND = 0V; T_amb = 25°C; t_r = t_f = 2.5ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL UNIT
t_PHL/t_PLH
Propagation delay
An, Bn to Bn, An
V_CC = 2.5V, C_L = 30pF
V_CC = 3.3V, C_L = 50pF
2.8
ns
3.0
C_I/O
Input/output capacitance
8.0
pF
C_I
Input capacitance
4.0
pF
C_PD
Power dissipation capacitance per
latch
V_I = GND to V_CC1
Outputs enabled
21
pF
Outputs disabled
3
NOTES:
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + S (C_L × V_CC2 × f_o) where: f_i = input frequency in MHz; C_L = output load capacitance in pF;
f_o = output frequency in MHz; V_CC = supply voltage in V; S (C_L × V_CC2 × f_o) = sum of outputs.
ORDERING INFORMATION
PACKAGES
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ALVCH16501 DGG
DWG NUMBER
SOT364-1
1998 Sep 29
2
853–2091 20106