74ALVCH162245 Datasheet, PDF (2/11 Pages) NXP Semiconductors – 16-bit bus transceiver with direction pin and 30ohm termination resistor 3-State

Philips Semiconductors
16-bit bus transceiver with direction pin and
30Ω termination resistor (3-State)
Product specification
74ALVCH162245
FEATURES
• Wide supply voltage range of 1.2V to 3.6V
• Complies with JEDEC standard no. 8-1A
• CMOS low power consumption
• MULTIBYTE^TM flow-through standard pin-out architecture
• Low inductance multiple V_CC and ground pins for minimum noise
and ground bounce
• Direct interface with TTL levels
• Bus hold on all data inputs
• Integrated 30Ω termination resistor
PIN CONFIGURATION
1DIR 1
1B0 2
1B1 3
GND 4
1B2 5
1B3 6
V_CC1 7
1B4 8
1B5 9
48 1OE
47 1A0
46 1A1
45 GND
44 1A2
43 1A3
42 V_CC2
41 1A4
40 1A5
DESCRIPTION
The 74ALVCH162245 is a 16-bit transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
The 74ALVCH162245 features two output enable (nOE) inputs for
easy cascading and two send/receive (nDIR) inputs for direction
control. nOE controls the outputs so that the buses are effectively
isolated. This device can be used as two 8-bit transceivers or one
16-bit transceiver.
The 74ALVCH162245 is designed with 30Ω series resistors in both
HIGH and LOW output states.
The 74ALVCH162245 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
GND 10
1B6 11
1B7 12
2B0 13
2B1 14
GND 15
2B2 16
2B3 17
V_CC1 18
2B4 19
2B5 20
GND 21
2B6 22
39 GND
38 1A6
37 1A7
36 2A0
35 2A1
34 GND
33 2A2
32 2A3
31 V_CC2
30 2A4
29 2A5
28 GND
27 2A6
2B7 23
26 2A7
2DIR 24
25 2OE
QUICK REFERENCE DATA
GND = 0V; T_amb = 25°C; t_r = t_f ≤ 2.5ns
SYMBOL
PARAMETER
CONDITIONS
SW00198
TYPICAL
t_PHL/t_PLH
C_I
C_I/O
C_PD
Propagation delay
An to Bn; Bn to An
Input capacitance
Input/output capacitance
Power dissipation capacitance per buffer
V_CC = 2.5V, C_L = 30pF
V_CC = 3.3V, C_L = 50pF
V_I = GND to V_CC1
2.4
4.0
8.0
Outputs enabled
27
Outputs disabled
4
NOTES:
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + S (C_L × V_CC2 × f_o) where: f_i = input frequency in MHz; C_L = output load capacitance in pF;
f_o = output frequency in MHz; V_CC = supply voltage in V; S (C_L × V_CC2 × f_o) = sum of the outputs.
UNIT
ns
pF
pF
pF
pF
ORDERING INFORMATION
PACKAGES
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
–40°C to +85°C
74ALVCH162245 DL
–40°C to +85°C
74ALVCH162245 DGG
NORTH AMERICA
ACH162245 DL
ACH162245 DGG
DWG NUMBER
SOT370-1
SOT362-1
1998 Jun 29
2
853-2085 19638