74ALVC16835A_15 Datasheet, PDF (2/12 Pages) NXP Semiconductors – 74ALVC16835A_15

Philips Semiconductors
18-bit registered driver (3-State)
Product specification
74ALVC16835A
FEATURES
• Wide supply voltage range of 1.2 V to 3.6 V
• Complies with JEDEC standard no. 8-1A.
• CMOS low power consumption
• Direct interface with TTL levels
• Current drive ± 24 mA at 3.0 V
• MULTIBYTE^TM flow-through standard pin-out architecture
• Low inductance multiple V_CC and GND pins for minimum noise
and ground bounce
• Output drive capability 50 Ω transmission lines @ 85°C
• Input diodes to accommodate strong drivers
DESCRIPTION
The 74ALVC16835A is a 18–bit registered driver. Data flow is
controlled by active low output enable (OE), active low latch enable
(LE) and clock inputs (CP).
When LE is LOW, the A to Y data flow is transparent. When LE is
HIGH and CP is held at LOW or HIGH, the data is latched; on the
LOW to HIGH transient of CP the A-data is stored in the
latch/flip-flop.
When OE is LOW the outputs are active. When OE is HIGH, the
outputs go to the high impedance OFF–state. Operation of the OE
input does not affect the state of the latch/flip-flop.
To ensure the high-impedance state during power up or power
down, OE should be tied to V_CC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
PIN CONFIGURATION
NC 1
NC 2
Y₁ 3
GND 4
Y₂ 5
Y₃ 6
V_CC 7
Y₄ 8
Y₅ 9
Y₆ 10
GND 11
Y₇ 12
Y₈ 13
Y₉ 14
Y₁₀ 15
Y₁₁ 16
Y₁₂ 17
GND 18
Y₁₃ 19
Y₁₄ 20
Y₁₅ 21
V_CC 22
Y₁₆ 23
Y₁₇ 24
GND 25
Y₁₈ 26
OE 27
LE 28
56 GND
55 NC
54 A₁
53 GND
52 A₂
51 A₃
50 V_CC
49 A₄
48 A₅
47 A₆
46 GND
45 A₇
44 A₈
43 A₉
42 A₁₀
41 A₁₁
40 A₁₂
39 GND
38 A₁₃
37 A₁₄
36 A₁₅
35 V_CC
34 A₁₆
33 A₁₇
32 GND
31 A₁₈
30 CP
29 GND
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25°C; t_r = t_f ≤ 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
SH00188
TYPICAL
Propagation delay
t_PHL/t_PLH
An to Yn;
LE to Yn;
V_CC = 3.3 V, C_L = 50 pF
2.3
2.6
CP to Yn
2.5
f_max
Maximum clock frequency
V_CC = 3.3 V, C_L = 50 pF
350
C_I
Input capacitance
4.0
C_I/O
Input/Output capacitance
8.0
C_PD
Power dissipation capacitance per buffer
V_I = GND to V_CC1
transparent mode
Output enabled
13
Output disabled
3
Clocked mode
Output enabled
22
Output disabled
15
NOTES:
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + S (C_L × V_CC2 × f_o) where: f_i = input frequency in MHz; C_L = output load capacitance in pF;
f_o = output frequency in MHz; V_CC = supply voltage in V; S (C_L × V_CC2 × f_o) = sum of outputs.
UNIT
ns
MHz
pF
pF
pF
2000 Mar 14
2
853–2190 23314