74ALS112A Datasheet, PDF (2/10 Pages) NXP Semiconductors – Dual J-K negative edge-triggered flip-flop

Philips Semiconductors
Dual J-K negative edge-triggered flip-flop
Product specification
74ALS112A
DESCRIPTION
The 74ALS112A, dual negative edge-triggered JK-type flip-flop
features individual J, K, clock (CPn), set (SD), and reset (RD)
inputs, true (Qn) and complementary (Qn) outputs.
The SD and RD inputs, when Low, set or reset the outputs as shown
in the function table regardless of the level at the other inputs.
A High level on the clock (CPn) input enables the J and K inputs and
data will be accepted. The logic levels at the J and K inputs may be
allowed to change while the CPn is High and the flip-flop will perform
according to the function table as long as minimum setup and hold
times are observed. Output changes are initiated by the High-to-Low
transition of the CPn.
TYPE
74ALS112A
TYPICAL
f_MAX
50MHz
TYPICAL
SUPPLY CURRENT
(TOTAL)
3.0mA
PIN CONFIGURATION
CP0 1
K0 2
J0 3
SD0 4
Q0 5
Q0 6
Q1 7
GND 8
16 V_CC
15 RD0
14 RD1
13 CP1
12 K1
11 J1
10 SD1
9 Q1
SF00103
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V_CC = 5V ±10%,
T_amb = 0°C to +70°C
16-pin plastic DIP
74ALS112AN
16-pin plastic SO
74ALS112AD
DRAWING
NUMBER
SOT38-4
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74ALS (U.L.)
HIGH/LOW
CP0, CP1
Clock Pulse input (active falling edge)
1.0/1.0
J0, J1
J inputs
1.0/2.0
K0, K1
K inputs
1.0/2.0
SD0, SD1
Set inputs (active-Low)
1.0/2.0
RD0, RD1
Reset inputs (active-Low)
1.0/2.0
Q0, Q1, Q0, Q1 Data outputs
20/80
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
LOGIC SYMBOL
IEC/IEEE SYMBOL
1
4
15
13
10
14
V_CC = Pin 16
GND = Pin 8
3 11 2 12
J0 J1 K0 K1
CP0
SD0
RD0
CP1
SD1
RD1
Q0 Q0 Q1 Q1
56 97
SF00104
3
1J
1
C1
2
1K
15
R
4
S
11
2J
13
C2
12
2K
14
R
10
S
LOAD VALUE
HIGH/LOW
20µA/0.1mA
20µA/0.2mA
20µA/0.2mA
20µA/0.2mA
20µA/0.2mA
0.4mA/8mA
5
6
9
7
SF00105
1996 Jun 27
2
853-1846 16995