74AHC74 Datasheet, PDF (2/20 Pages) NXP Semiconductors – Dual D-type flip-flop with set and reset; positive-edge trigger

Philips Semiconductors
Dual D-type flip-flop with set and reset;
positive-edge trigger
Product specification
74AHC74; 74AHCT74
FEATURES
• ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
• Balanced propagation delays
• Inputs accepts voltages higher than
V_CC
• For AHC only:
operates with CMOS input levels
• For AHCT only:
operates with TTL input levels
• Output capability: standard
• I_CC category: flip-flops
• Specified from
−40 to +85 and +125 °C.
DESCRIPTION
The 74AHC/AHCT74 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
No. 7A.
The 74AHC/AHCT74 dual
positive-edge triggered, D-type
flip-flops with individual data (D)
inputs, clock (CP) inputs, set (S_D) and
reset (R_D) inputs; also
complementary Q and Q outputs.
The set and reset are asynchronous
active LOW inputs and operate
independently of the clock input.
Information on the data input is
transferred to the Q output on the
LOW-to-HIGH transition of the clock
pulse. The D inputs must be stable
one set-up time prior to the
LOW-to-HIGH clock transition for
predictable operation.
Schmitt-trigger action in the clock
input makes the circuit highly tolerant
to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f ≤ 3.0 ns.
SYMBOL
PARAMETER
TYPICAL
CONDITIONS
UNIT
AHC AHCT
t_PHL/t_PLH propagation delay
nCP to nQ, nQ
C_L = 15 pF;
V_CC = 5 V
3.7 3.3
nS_D, nR_D to nQ, nQ
3.7 3.7
f_max
max. clock frequency
130 100
C_I
input capacitance
V_I = V_CC or GND 4.0 4.0
C_PD
power dissipation
C_L = 50 pF;
12 16
capacitance
f = 1 MHz;
notes 1 and 2
ns
ns
MHz
pF
pF
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW).
P_D = C_PD × V_CC2 × f_i + ∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz; f_o = output frequency in MHz;
∑ (C_L × V_CC2 × f_o) = sum of outputs;
C_L = output load capacitance in pF;
V_CC = supply voltage in Volts.
2. The condition is V_I = GND to V_CC.
FUNCTION TABLES
Table 1 See note 1
INPUT
nS_D
nR_D
nCP
nD
L
H
X
X
H
L
X
X
L
L
X
X
OUTPUT
nQ
nQ
H
L
L
H
H
H
Table 2 See note 1
INPUT
OUTPUT
nS_D
nR_D
nCP
nD
nQ_n+1
nQ_n+1
H
H
↑
L
L
H
H
H
↑
H
H
L
Note to Tables 1 and 2
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑ = LOW-to-HIGH CP transition;
Q_n+1 = state after the next LOW-to-HIGH CP transition.
1999 Sep 23
2