74AHC257 Datasheet, PDF (2/20 Pages) NXP Semiconductors – Quad 2-input multiplexer; 3-state

Philips Semiconductors
Quad 2-input multiplexer; 3-state
Product specification
74AHC257;
74AHCT257
FEATURES
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
• Balanced propagation delays
• All inputs have Schmitt-trigger actions
• Non-inverting data path
• Inputs accept voltages higher than V_CC
• For AHC only: operates with CMOS input levels
• For AHCT only: operates with TTL input levels
• Specified from −40 to +85 °C and −40 to +125 °C.
DESCRIPTION
The 74AHC/AHCT257 are high-speed Si-gate CMOS
devices and are pin compatible with Low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
The 74AHC/AHCT257 has four identical 2-input
multiplexers with 3-state outputs, which select 4 bits of
data from two sources and are controlled by a common
data select input (S).
The data inputs from source 0 (1I₀ to 4I₀) are selected
when input S is LOW and the data inputs from source 1
(1I₁ to 4I₁) are selected when S is HIGH. Data appears at
the outputs (1Y to 4Y) in true (non-inverting) form from the
selected inputs.
The 74AHC/AHCT257 is the logic implementation of a
4-pole 2-position switch, where the position of the switch is
determined by the logic levels applied to S. The outputs
are forced to a high impedance OFF-state when OE is
HIGH.
If OE is LOW then the logic equations for the outputs are:
1Y = 1I₁ × S + 1I₀ × S;
2Y = 2I₁ × S + 2I₀ × S;
3Y = 3I₁ × S + 3I₀ × S;
4Y = 4I₁ × S + 4I₀ × S.
The ‘257’ is identical to the ‘258’ but has non-inverting
(true) outputs.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f ≤ 3.0 ns.
SYMBOL
PARAMETER
t_PHL/t_PLH
C_I
C_O
C_PD
propagation delay
nl₀, nI₁ to nY
S to nY
input capacitance
output capacitance
power dissipation
capacitance
CONDITIONS
TYPICAL
AHC AHCT
UNIT
C_L = 15 pF; V_CC = 5 V
2.9
3.7
ns
C_L = 15 pF; V_CC = 5 V
3.5
5.1
ns
V_I = V_CC or GND
3.0
3.0
pF
4.0
4.0
pF
C_L = 50 pF; f_i = 1 MHz; notes 1 and 2
4 outputs switching via input S
45
51
pF
1 output switching via input I
15
15
pF
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW).
P_D = C_PD × V_CC2 × f_i + ∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz;
f_o = output frequency in MHz;
∑ (C_L × V_CC2 × f_o) = sum of outputs;
C_L = output load capacitance in pF;
V_CC = supply voltage in Volts.
2. The condition is V_I = GND to V_CC.
2000 Apr 03
2