74AHC138 Datasheet, PDF (2/16 Pages) NXP Semiconductors – 3-to-8 line decoder/demultiplexer; inverting

Philips Semiconductors
3-to-8 line decoder/demultiplexer; inverting
Product specification
74AHC138;
74AHCT138
FEATURES
• ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
• Balanced propagation delays
• All inputs have Schmitt-trigger
actions
• Multiple input enable for easy
expansion
• Ideal for memory chip select
decoding
• Inputs accept voltages higher than
V_CC
• For AHC only:
operates with CMOS input levels
• For AHCT only:
operates with TTL input levels
• Specified from
−40 to +85 and +125 °C.
DESCRIPTION
The 74AHC/AHCT138 are high-speed Si-gate CMOS devices and are pin
compatible with low power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard No. 7A.
The 74AHC/AHCT138 decoders accept three binary weighted address inputs
(A₀, A₁ and A₂) and when enabled, provide 8 mutually exclusive active LOW
outputs (Y₀ to Y₇).
The ‘138’ features three enable inputs: two active LOW (E₁ and E₂) and one
active HIGH (E₃). Every output will be HIGH unless E₁ and E₂ are LOW and E₃
is HIGH.
This multiple enable function allows easy parallel expansion of the ‘138’ to a
1-of-32 (5 to 32 lines) decoder with just four ‘138’ ICs and one inverter.
The ‘138’ can be used as an eight output demultiplexer by using one of the
active LOW enable inputs as the data input and the remaining enable inputs as
strobes. Unused enable inputs must be permanently tied to their appropriate
active HIGH or LOW state.
The ‘138’ is identical to the ‘238’ but has inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f ≤ 3.0 ns.
SYMBOL
PARAMETER
CONDITIONS
t_PHL/t_PLH
C_I
C_O
C_PD
propagation delay A_n to Y_n
propagation delay E₃ to Y_n; E_n to Y_n
input capacitance
output capacitance
power dissipation capacitance
C_L = 15 pF; V_CC = 5 V
C_L = 15 pF; V_CC = 5 V
V_I = V_CC or GND
C_L = 50 pF; f = 1 MHz;
notes 1 and 2
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW).
P_D = C_PD × V_CC2 × f_i + ∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz;
f_o = output frequency in MHz;
∑ (C_L × V_CC2 × f_o) = sum of outputs;
C_L = output load capacitance in pF;
V_CC = supply voltage in Volts.
2. The condition is V_I = GND to V_CC.
TYPICAL
AHC
4.4
4.2
3.0
4.0
18
AHCT
4.4
4.3
3.0
4.0
23
UNIT
ns
ns
pF
pF
pF
1999 Sep 27
2