74ABT16841A Datasheet, PDF (2/10 Pages) NXP Semiconductors – 20-bit bus interface latch 3-State

Philips Semiconductors
20-bit bus interface latch (3-State)
Product specification
74ABT16841A
74ABTH16841A
FEATURES
• High speed parallel latches
• Live insertion/extraction permitted
• Extra data width for wide address/data paths or buses carrying
parity
• Power-up 3-State
• 74ABTH16841A incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs
• Power-up reset
• Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
• Output capability: +64mA/–32mA
• Latch-up protection exceeds 500mA per Jedec Std 17
• ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The 74ABT16841A Bus interface latch is designed to provide extra
data width for wider data/address paths of buses carrying parity.
The 74ABT16841A consists of two sets of ten D-type latches with
3-State outputs. The flip-flops appear transparent to the data when
Latch Enable (nLE) is High. This allows asynchronous operation, as
the output transition follows the data in transition. On the nLE
High-to-Low transition, the data that meets the setup and hold time
is latched.
Data appears on the bus when the Output Enable (nOE) is Low.
When nOE is High the output is in the High-impedance state.
Two options are available, 74ABT16841A which does not have the
bus-hold feature and 74ABTH16841A which incorporates the
bus-hold feature.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
t_PLH
t_PHL
C_IN
C_OUT
I_CCZ
I_CCL
Propagation delay
nDx to nQx
Input capacitance
Output capacitance
Quiescent supply current
CONDITIONS
T_amb = 25°C; GND = 0V
C_L = 50pF; V_CC = 5V
V_I = 0V or V_CC
V_O = 0V or V_CC; 3-State
Outputs disabled; V_CC = 5.5V
Outputs LOW; V_CC = 5.5V
TYPICAL UNIT
3.1
2.2
ns
4
pF
7
pF
500
µA
10
mA
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
–40°C to +85°C
74ABT16841A DL
–40°C to +85°C
74ABT16841A DGG
–40°C to +85°C
74ABTH16841A DL
–40°C to +85°C
74ABTH16841A DGG
NORTH AMERICA
BT16841A DL
BT16841A DGG
BH16841A DL
BH16841A DGG
DWG NUMBER
SOT371-1
SOT364-1
SOT371-1
SOT364-1
PIN DESCRIPTION
PIN NUMBER
55, 54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31, 30
2, 3, 5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24, 26, 27
1, 28
56, 29
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
SYMBOL
1D0 – 1D9
2D0 – 2D9
1Q0 – 1Q9
2Q0 – 2Q9
1OE, 2OE
1LE, 2LE
GND
V_CC
Data inputs
FUNCTION
Data outputs
Output enable inputs (active-Low)
Latch enable inputs (active rising edge)
Ground (0V)
Positive supply voltage
1998 Feb 27
2
853-1797 19025