SAB9077H Datasheet, PDF (19/32 Pages) NXP Semiconductors – Picture-In-Picture PIP controller

Philips Semiconductors
Picture-In-Picture (PIP) controller
Preliminary specification
SAB9077H
Additional I²C-bus settings
Table 6 Overview of additional I²C-bus sub-addresses
SA
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
DATA BYTE
BIT 7
PRIO
MHRPO31
MHRPN31
MHPIC7
MVPIC7
MHDIS07
MHDIS17
MHDIS27
MHDIS37
MVDIS7
SHRPO31
SHRPN31
SHPIC7
SVPIC7
SHDIS07
SHDIS17
SHDIS27
SHDIS37
SVDIS7
BIT 6
DPAL
MHRPO30
MHRPN30
MHPIC6
MVPIC6
MHDIS06
MHDIS16
MHDIS26
MHDIS36
MVDIS6
SHRPO30
SHRPN30
SHPIC6
SVPIC6
SHDIS06
SHDIS16
SHDIS26
SHDIS36
SVDIS6
BIT 5
MPAL
MHRPO21
MHRPN21
MHPIC5
MVPIC5
MHDIS05
MHDIS15
MHDIS25
MHDIS35
MVDIS5
SHRPO21
SHRPN21
SHPIC5
SVPIC5
SHDIS05
SHDIS15
SHDIS25
SHDIS35
SVDIS5
BIT 4
SPAL
MHRPO20
MHRPN20
MHPIC4
MVPIC4
MHDIS04
MHDIS14
MHDIS24
MHDIS34
MVDIS4
SHRPO20
SHRPN20
SHPIC4
SVPIC4
SHDIS04
SHDIS14
SHDIS24
SHDIS34
SVDIS4
BIT 3
MVRPN1
MHRPO11
MHRPN11
MHPIC3
MVPIC3
MHDIS03
MHDIS13
MHDIS23
MHDIS33
MVDIS3
SHRPO11
SHRPN11
SHPIC3
SVPIC3
SHDIS03
SHDIS13
SHDIS23
SHDIS33
SVDIS3
BIT 2
MVRPN0
MHRPO10
MHRPN10
MHPIC2
MVPIC2
MHDIS02
MHDIS12
MHDIS22
MHDIS32
MVDIS2
SHRPO10
SHRPN10
SHPIC2
SVPIC2
SHDIS02
SHDIS12
SHDIS22
SHDIS32
SVDIS2
BIT 1
SVRPN1
MHRPO1
MHRPN1
MHPIC1
MVPIC1
MHDIS01
MHDIS11
MHDIS21
MHDIS31
MVDIS1
SHRPO01
SHRPN01
SHPIC1
SVPIC1
SHDIS01
SHDIS11
SHDIS21
SHDIS31
SVDIS1
BIT 0
SVRPN0
MHRPO0
MHRPN0
MHPIC0
MVPIC0
MHDIS00
MHDIS10
MHDIS20
MHDIS30
MVDIS0
SHRPO00
SHRPN00
SHPIC0
SVPIC0
SHDIS00
SHDIS10
SHDIS20
SHDIS30
SVDIS0
Additional I²C-bus register and PIP modes become
available in sub addresses 20H to 32H.
An overview of these I²C-bus registers is given in Table 6.
The meaning and relation of the I²C-bus registers is shown
in Fig.8. The background has a fixed size and can be fine
positioned with BGHFP and BGVFP bits. The shown PIPs
are only for one channel (main or sub), the other channel
has the same control and can be displayed at the same
time. The SDHFP and MDHFP bits determine the most left
shown pixel for this channel in 256 steps of 4 pixels.
The SDVFP and MDVFP bits determine the most upper
shown pixel for this channel in 256 steps of 1 line.
The SHPIC and MHPIC bits determine the horizontal
picture size in 256 steps of 4 pixels, the minimum value is
4 pixels. The SVPIC and MVPIC bits determine the vertical
picture size in 256 steps of 1 line, the minimum value is
1 line. The PIP mode is built-up of a maximum of four
horizontal rows. The minimum is one row, more rows can
be displayed by setting the vertical repetition rate number
VRPN bits.
The distance between the rows can be set by the SVDIS
and MVDIS bits. Every row is built-up of a maximum of four
PIPs. The minimum is one PIP, additional PIPs can be
added with the HRPN values. The SHRPO and MHRPO
bits determine the offset distance between the starting
points of the first PIP. The distances between the starting
points of the PIPs on a row are determined by the SHDIS
and MHDIS bits.
SA 20H CONTROL REGISTER
The PRIO bit sets the priority between main and sub
channel. If PRIO is set to logic 0 priority is given to the sub
channel which means that the sub channel PIPs, if
present, are placed on top of the main PIPs. If PRIO is set
to logic 1 it places the main PIPs on top of the sub PIPs.
The DPAL bit sets the correct default values for PAL on the
display side. The background is enlarged from
238 lines/field to 288 lines/field.
1996 Aug 07
19